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| -rw-r--r-- | docs/UsingLibraries.html | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/docs/UsingLibraries.html b/docs/UsingLibraries.html index 490fd1a517..8aa99699b7 100644 --- a/docs/UsingLibraries.html +++ b/docs/UsingLibraries.html @@ -72,20 +72,24 @@ <table style="text-align:left"> <tr><th>Library</th><th>Forms</th><th>Description</th></tr> <tr><th colspan="3">Core Libraries</th></tr> + <tr><td>LLVMArchive</td><td><tt>.a</tt></td> + <td>LLVM archive reading and writing</td></tr> <tr><td>LLVMAsmParser</td><td><tt>.o</tt></td> - <td>LLVM Assembly Parsing</td></tr> + <td>LLVM assembly parsing</td></tr> <tr><td>LLVMBCReader</td><td><tt>.o</tt></td> - <td>LLVM Bytecode Reading</td></tr> + <td>LLVM bytecode reading</td></tr> <tr><td>LLVMBCWriter</td><td><tt>.o</tt></td> - <td>LLVM Bytecode Writing</td></tr> + <td>LLVM bytecode writing</td></tr> + <tr><td>LLVMCore</td><td><tt>.o</tt></td> + <td>LLVM core intermediate representation</td></tr> <tr><td>LLVMDebugger</td><td><tt>.o</tt></td> - <td>Source Level Debugging Support</td></tr> + <td>Source level debugging support</td></tr> + <tr><td>LLVMLinker</td><td><tt>.a</tt></td> + <td>Bytecode and archive linking interface</td></tr> <tr><td>LLVMSupport</td><td><tt>.a .o</tt></td> <td>General support utilities</td></tr> <tr><td>LLVMSystem</td><td><tt>.a .o</tt></td> - <td>Operating system abstraction</td></tr> - <tr><td>LLVMCore</td><td><tt>.o</tt></td> - <td>LLVM Core IR</td></tr> + <td>Operating system abstraction layer</td></tr> <tr><th colspan="3">Analysis Libraries</th></tr> <tr><td>LLVMAnalysis</td><td><tt>.a .o</tt></td> @@ -119,9 +123,11 @@ <tr><td>LLVMPowerPC</td><td><tt>.o</tt></td> <td>PowerPC code generation backend</td></tr> <tr><td>LLVMSelectionDAG</td><td><tt>.o</tt></td> - <td>Aggressive instruction selector for Directed Acyclic Graphs.</td></tr> + <td>Aggressive instruction selector for directed acyclic graphs.</td></tr> <tr><td>LLVMSkeleton</td><td><tt>.a .o</tt></td> <td>Skeleton for a code generation backend.</td></tr> + <tr><td>LLVMSparcV8</td><td><tt>.o</tt></td> + <td>Code generation for SparcV8.</td></tr> <tr><td>LLVMSparcV9</td><td><tt>.o</tt></td> <td>Code generation for SparcV9.</td></tr> <tr><td>LLVMSparcV9RegAlloc</td><td><tt>.a .o</tt></td> |