diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 11 | ||||
| -rw-r--r-- | test/CodeGen/X86/legalize-shift-64.ll | 11 |
2 files changed, 20 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 5da6d29aab..e08dd6dcb6 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -2095,9 +2095,16 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, // Expand the subcomponents. SDValue LHSL, LHSH; GetExpandedInteger(N->getOperand(0), LHSL, LHSH); - - SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; EVT VT = LHSL.getValueType(); + + // If the shift amount operand is coming from a vector legalization it may + // not have the right return type. Fix that first by casting the operand. + SDValue ShiftOp = N->getOperand(1); + MVT ShiftTy = TLI.getShiftAmountTy(VT); + if (ShiftOp.getValueType() != ShiftTy) + ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); + + SDValue Ops[] = { LHSL, LHSH, ShiftOp }; Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3); Hi = Lo.getValue(1); return; diff --git a/test/CodeGen/X86/legalize-shift-64.ll b/test/CodeGen/X86/legalize-shift-64.ll index c9f2fc27db..71ef2d3152 100644 --- a/test/CodeGen/X86/legalize-shift-64.ll +++ b/test/CodeGen/X86/legalize-shift-64.ll @@ -54,3 +54,14 @@ define i64 @test4(i64 %xx, i32 %test) nounwind { ; CHECK: orl %esi, %eax ; CHECK: sarl %cl, %edx } + +; PR14668 +define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) { + %shl = shl <2 x i64> %A, %B + ret <2 x i64> %shl +; CHECK: test5 +; CHECK: shl +; CHECK: shldl +; CHECK: shl +; CHECK: shldl +} |