diff options
| -rw-r--r-- | lib/Target/Mips/MipsCondMov.td | 10 | ||||
| -rwxr-xr-x | test/CodeGen/Mips/cmov.ll | 20 |
2 files changed, 30 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsCondMov.td b/lib/Target/Mips/MipsCondMov.td index da336804e5..40f0958bdc 100644 --- a/lib/Target/Mips/MipsCondMov.td +++ b/lib/Target/Mips/MipsCondMov.td @@ -83,6 +83,12 @@ multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC, (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>; } +multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC, + Instruction MOVZInst, Instruction XORiOp> { + def : Pat<(select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F), + (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>; +} + multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst, Instruction XOROp> { def : Pat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), @@ -170,6 +176,7 @@ let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in { // Instantiation of conditional move patterns. defm : MovzPats0<CPURegs, CPURegs, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>; defm : MovzPats1<CPURegs, CPURegs, MOVZ_I_I, XOR>; +defm : MovzPats2<CPURegs, CPURegs, MOVZ_I_I, XORi>; let Predicates = [HasMips64] in { defm : MovzPats0<CPURegs, CPU64Regs, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>; defm : MovzPats0<CPU64Regs, CPURegs, MOVZ_I_I, SLT64, SLTu64, SLTi64, @@ -179,6 +186,9 @@ let Predicates = [HasMips64] in { defm : MovzPats1<CPURegs, CPU64Regs, MOVZ_I_I64, XOR>; defm : MovzPats1<CPU64Regs, CPURegs, MOVZ_I64_I, XOR64>; defm : MovzPats1<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XOR64>; + defm : MovzPats2<CPURegs, CPU64Regs, MOVZ_I_I64, XORi>; + defm : MovzPats2<CPU64Regs, CPURegs, MOVZ_I64_I, XORi64>; + defm : MovzPats2<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XORi64>; } defm : MovnPats<CPURegs, CPURegs, MOVN_I_I, XOR>; diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll index 86bf337080..c8210033ce 100755 --- a/test/CodeGen/Mips/cmov.ll +++ b/test/CodeGen/Mips/cmov.ll @@ -37,3 +37,23 @@ entry: ret i32 %cond } +; O32: cmov3: +; O32: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234 +; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]] +define i32 @cmov3(i32 %a, i32 %b, i32 %c) nounwind readnone { +entry: + %cmp = icmp eq i32 %a, 234 + %cond = select i1 %cmp, i32 %b, i32 %c + ret i32 %cond +} + +; N64: cmov4: +; N64: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234 +; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]] +define i64 @cmov4(i32 %a, i64 %b, i64 %c) nounwind readnone { +entry: + %cmp = icmp eq i32 %a, 234 + %cond = select i1 %cmp, i64 %b, i64 %c + ret i64 %cond +} + |