diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.td | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index d6e8175009..8324b9439d 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -73,14 +73,17 @@ def TBL : SPR<4>; def TBU : SPR<5>; /// Register classes +// Allocate volatiles first +// then nonvolatiles in reverse order since stmw/lmw save from rN to r31 def GPRC : RegisterClass<i32, 4, - [R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, - R26, R27, R28, R29, R30, R31, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10]> + [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, + R31, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, + R16, R15, R14, R13, R0, R1]> { let Methods = [{ iterator allocation_order_end(MachineFunction &MF) const { - return end()-10; // do not allocate r0-r10 + return end()-2; } }]; } @@ -89,4 +92,4 @@ def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>; -//def CRRC : RegisterClass<i4, 1, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>; +//def CRRC : RegisterClass<i32, 4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>; |