diff options
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 30 | ||||
| -rw-r--r-- | test/CodeGen/Mips/mips64instrs.ll | 36 |
2 files changed, 66 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 764669e1aa..a42b404d13 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -18,6 +18,18 @@ def HasMips64 : Predicate<"Subtarget.hasMips64()">; def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">; //===----------------------------------------------------------------------===// +// Mips Operand, Complex Patterns and Transformations Definitions. +//===----------------------------------------------------------------------===// + +// Instruction operand types +def simm16_64 : Operand<i64>; + +// Unsigned Operand +def uimm16_64 : Operand<i64> { + let PrintMethod = "printUnsignedImm"; +} + +//===----------------------------------------------------------------------===// // Instructions specific format //===----------------------------------------------------------------------===// @@ -30,6 +42,13 @@ class ArithR64<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode, let isCommutable = isComm; } +// Arithmetic 2 register operands +class ArithI64<bits<6> op, string instr_asm, SDNode OpNode, + Operand Od, PatLeaf imm_type> : + FI<op, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, Od:$c), + !strconcat(instr_asm, "\t$dst, $b, $c"), + [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, imm_type:$c))], IIAlu>; + // Logical let isCommutable = 1 in class LogicR64<bits<6> func, string instr_asm, SDNode OpNode>: @@ -37,10 +56,21 @@ class LogicR64<bits<6> func, string instr_asm, SDNode OpNode>: !strconcat(instr_asm, "\t$dst, $b, $c"), [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], IIAlu>; +class LogicI64<bits<6> op, string instr_asm, SDNode OpNode>: + FI<op, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, uimm16_64:$c), + !strconcat(instr_asm, "\t$dst, $b, $c"), + [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, immZExt16:$c))], IIAlu>; + //===----------------------------------------------------------------------===// // Instruction definition //===----------------------------------------------------------------------===// +/// Arithmetic Instructions (ALU Immediate) +def DADDiu : ArithI64<0x19, "daddiu", add, simm16_64, immSExt16>; +def DANDi : LogicI64<0x0c, "andi", and>; +def DORi : LogicI64<0x0d, "ori", or>; +def DXORi : LogicI64<0x0e, "xori", xor>; + /// Arithmetic Instructions (3-Operand, R-Type) def DADDu : ArithR64<0x00, 0x2d, "daddu", add, IIAlu, 1>; def DSUBu : ArithR64<0x00, 0x2f, "dsubu", sub, IIAlu, 1>; diff --git a/test/CodeGen/Mips/mips64instrs.ll b/test/CodeGen/Mips/mips64instrs.ll index 1adf1379f6..8cbb5b947e 100644 --- a/test/CodeGen/Mips/mips64instrs.ll +++ b/test/CodeGen/Mips/mips64instrs.ll @@ -34,3 +34,39 @@ entry: %xor = xor i64 %a1, %a0 ret i64 %xor } + +define i64 @f7(i64 %a0) nounwind readnone { +entry: +; CHECK: daddiu + %add = add nsw i64 %a0, 20 + ret i64 %add +} + +define i64 @f8(i64 %a0) nounwind readnone { +entry: +; CHECK: daddiu + %sub = add nsw i64 %a0, -20 + ret i64 %sub +} + +define i64 @f9(i64 %a0) nounwind readnone { +entry: +; CHECK: andi + %and = and i64 %a0, 20 + ret i64 %and +} + +define i64 @f10(i64 %a0) nounwind readnone { +entry: +; CHECK: ori + %or = or i64 %a0, 20 + ret i64 %or +} + +define i64 @f11(i64 %a0) nounwind readnone { +entry: +; CHECK: xori + %xor = xor i64 %a0, 20 + ret i64 %xor +} + |