diff options
| -rw-r--r-- | include/llvm/IntrinsicsXCore.td | 10 | ||||
| -rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.td | 26 | ||||
| -rw-r--r-- | test/CodeGen/XCore/resources.ll | 40 |
3 files changed, 74 insertions, 2 deletions
diff --git a/include/llvm/IntrinsicsXCore.td b/include/llvm/IntrinsicsXCore.td index 97bac1d2da..f42511b380 100644 --- a/include/llvm/IntrinsicsXCore.td +++ b/include/llvm/IntrinsicsXCore.td @@ -33,4 +33,14 @@ let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.". [NoCapture<0>]>; def int_xcore_setc : Intrinsic<[],[llvm_anyptr_ty, llvm_i32_ty], [NoCapture<0>]>; + def int_xcore_inshr : Intrinsic<[llvm_i32_ty],[llvm_anyptr_ty, llvm_i32_ty], + [NoCapture<0>]>; + def int_xcore_outshr : Intrinsic<[llvm_i32_ty],[llvm_anyptr_ty, llvm_i32_ty], + [NoCapture<0>]>; + def int_xcore_setpt : Intrinsic<[],[llvm_anyptr_ty, llvm_i32_ty], + [NoCapture<0>]>; + def int_xcore_getts : Intrinsic<[llvm_i32_ty],[llvm_anyptr_ty], + [NoCapture<0>]>; + def int_xcore_syncr : Intrinsic<[],[llvm_anyptr_ty], + [NoCapture<0>]>; } diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index 38cc734ce7..bf32728780 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -727,7 +727,7 @@ def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>; -// TODO setd, eet, eef, getts, setpt, outshr, inshr, testwct, tinitpc, tinitdp, +// TODO setd, eet, eef, testwct, tinitpc, tinitdp, // tinitsp, tinitcp, tsetmr, sext (reg), zext (reg) let Constraints = "$src1 = $dst" in { let neverHasSideEffects = 1 in @@ -758,6 +758,14 @@ def GETR_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$type), "getr $dst, $type", [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>; +def GETTS_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), + "getts $dst, res[$r]", + [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>; + +def SETPT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), + "setpt res[$r], $val", + [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>; + def OUTCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), "outct res[$r], $val", [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>; @@ -774,6 +782,11 @@ def OUT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), "out res[$r], $val", [(int_xcore_out GRRegs:$r, GRRegs:$val)]>; +let Constraints = "$src = $dst" in +def OUTSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src), + "outshr res[$r], $src", + [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>; + def INCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), "inct $dst, res[$r]", [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>; @@ -786,6 +799,11 @@ def IN_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), "in $dst, res[$r]", [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>; +let Constraints = "$src = $dst" in +def INSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src), + "inshr $dst, res[$r]", + [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>; + def CHKCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), "chkct res[$r], $val", [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>; @@ -818,7 +836,7 @@ def SETC_l2r : _FRU6<(outs), (ins GRRegs:$r, GRRegs:$val), [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>; // One operand short -// TODO edu, eeu, waitet, waitef, tstart, msync, mjoin, syncr, clrtp +// TODO edu, eeu, waitet, waitef, tstart, msync, mjoin, clrtp // setdp, setcp, setv, setev, kcall // dgetreg let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in @@ -859,6 +877,10 @@ def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops), [(XCoreBranchLink GRRegs:$addr)]>; } +def SYNCR_1r : _F1R<(outs), (ins GRRegs:$r), + "syncr res[$r]", + [(int_xcore_syncr GRRegs:$r)]>; + def FREER_1r : _F1R<(outs), (ins GRRegs:$r), "freer res[$r]", [(int_xcore_freer GRRegs:$r)]>; diff --git a/test/CodeGen/XCore/resources.ll b/test/CodeGen/XCore/resources.ll index 3114bdcd17..b7cda58902 100644 --- a/test/CodeGen/XCore/resources.ll +++ b/test/CodeGen/XCore/resources.ll @@ -11,6 +11,11 @@ declare void @llvm.xcore.outct.p1i8(i8 addrspace(1)* %r, i32 %value) declare void @llvm.xcore.chkct.p1i8(i8 addrspace(1)* %r, i32 %value) declare void @llvm.xcore.setd.p1i8(i8 addrspace(1)* %r, i32 %value) declare void @llvm.xcore.setc.p1i8(i8 addrspace(1)* %r, i32 %value) +declare i32 @llvm.xcore.inshr.p1i8(i8 addrspace(1)* %r, i32 %value) +declare i32 @llvm.xcore.outshr.p1i8(i8 addrspace(1)* %r, i32 %value) +declare void @llvm.xcore.setpt.p1i8(i8 addrspace(1)* %r, i32 %value) +declare i32 @llvm.xcore.getts.p1i8(i8 addrspace(1)* %r) +declare void @llvm.xcore.syncr.p1i8(i8 addrspace(1)* %r) define i8 addrspace(1)* @getr() { ; CHECK: getr: @@ -109,3 +114,38 @@ define void @setci(i8 addrspace(1)* %r) { call void @llvm.xcore.setc.p1i8(i8 addrspace(1)* %r, i32 2) ret void } + +define i32 @inshr(i32 %value, i8 addrspace(1)* %r) { +; CHECK: inshr: +; CHECK: inshr r0, res[r1] + %result = call i32 @llvm.xcore.inshr.p1i8(i8 addrspace(1)* %r, i32 %value) + ret i32 %result +} + +define i32 @outshr(i32 %value, i8 addrspace(1)* %r) { +; CHECK: outshr: +; CHECK: outshr res[r1], r0 + %result = call i32 @llvm.xcore.outshr.p1i8(i8 addrspace(1)* %r, i32 %value) + ret i32 %result +} + +define void @setpt(i8 addrspace(1)* %r, i32 %value) { +; CHECK: setpt: +; CHECK: setpt res[r0], r1 + call void @llvm.xcore.setpt.p1i8(i8 addrspace(1)* %r, i32 %value) + ret void +} + +define i32 @getts(i8 addrspace(1)* %r) { +; CHECK: getts: +; CHECK: getts r0, res[r0] + %result = call i32 @llvm.xcore.getts.p1i8(i8 addrspace(1)* %r) + ret i32 %result +} + +define void @syncr(i8 addrspace(1)* %r) { +; CHECK: syncr: +; CHECK: syncr res[r0] + call void @llvm.xcore.syncr.p1i8(i8 addrspace(1)* %r) + ret void +} |