diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 12 | ||||
| -rw-r--r-- | test/MC/ARM/neon-bitwise-encoding.ll | 58 |
2 files changed, 70 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index a0f9a4b29f..2e40d0e09a 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -1765,6 +1765,18 @@ class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, let Inst{11-8} = op11_8; let Inst{6} = op6; let Inst{4} = op4; + + // Instruction operands. + bits<5> Vd; + bits<5> Vn; + bits<5> Vm; + + let Inst{15-12} = Vd{3-0}; + let Inst{22} = Vd{4}; + let Inst{19-16} = Vn{3-0}; + let Inst{7} = Vn{4}; + let Inst{3-0} = Vm{3-0}; + let Inst{5} = Vm{4}; } // NEON VMOVs between scalar and core registers. diff --git a/test/MC/ARM/neon-bitwise-encoding.ll b/test/MC/ARM/neon-bitwise-encoding.ll new file mode 100644 index 0000000000..2a77576867 --- /dev/null +++ b/test/MC/ARM/neon-bitwise-encoding.ll @@ -0,0 +1,58 @@ +; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s + +; FIXME: The following instructions still require testing: +; - vand with immediate + +; CHECK: vand_8xi8 +define <8 x i8> @vand_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B +; CHECK: vand d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf2] + %tmp3 = and <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +; CHECK: vand_16xi8 +define <16 x i8> @vand_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B +; CHECK: vand q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xf2] + %tmp3 = and <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +; CHECK: veor_8xi8 +define <8 x i8> @veor_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B +; CHECK: veor d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf3] + %tmp3 = xor <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +; CHECK: veor_16xi8 +define <16 x i8> @veor_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B +; CHECK: veor q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xf3] + %tmp3 = xor <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +; CHECK: vorr_8xi8 +define <8 x i8> @vorr_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B +; CHECK: vorr d16, d17, d16 @ encoding: [0xb0,0x01,0x61,0xf2] + %tmp3 = or <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +; CHECK: vorr_16xi8 +define <16 x i8> @vorr_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B +; CHECK: vorr q8, q8, q9 @ encoding: [0xf2,0x01,0x60,0xf2] + %tmp3 = or <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +}
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