diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 6 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 6 | ||||
| -rw-r--r-- | test/MC/ARM/basic-arm-instructions.s | 12 |
3 files changed, 18 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 322f700b36..3c1ff6c7d0 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -442,14 +442,14 @@ class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, let Inst{3-0} = Rt; } class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> - : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> { + : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> { bits<4> Rt; bits<4> Rt2; - bits<4> Rn; + bits<4> addr; let Inst{27-23} = 0b00010; let Inst{22} = b; let Inst{21-20} = 0b00; - let Inst{19-16} = Rn; + let Inst{19-16} = addr; let Inst{15-12} = Rt; let Inst{11-4} = 0b00001001; let Inst{3-0} = Rt2; diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index c3b11442d3..c5860ab280 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -3659,10 +3659,10 @@ def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", let Inst{31-0} = 0b11110101011111111111000000011111; } -// SWP/SWPB are deprecated in V6/V7 and for disassembly only. +// SWP/SWPB are deprecated in V6/V7. let mayLoad = 1, mayStore = 1 in { -def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp", []>; -def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb", []>; +def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addrmode7:$addr), "swp", []>; +def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addrmode7:$addr), "swpb", []>; } //===----------------------------------------------------------------------===// diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 13afd8b583..adbdf9e596 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -1763,3 +1763,15 @@ _func: @ CHECK: svc #16 @ encoding: [0x10,0x00,0x00,0xef] @ CHECK: svc #0 @ encoding: [0x00,0x00,0x00,0xef] @ CHECK: svc #16777215 @ encoding: [0xff,0xff,0xff,0xef] + + +@------------------------------------------------------------------------------ +@ SWP/SWPB +@------------------------------------------------------------------------------ + swp r1, r2, [r3] + swp r4, r4, [r6] + swpb r5, r1, [r9] + +@ CHECK: swp r1, r2, [r3] @ encoding: [0x92,0x10,0x03,0xe1] +@ CHECK: swp r4, r4, [r6] @ encoding: [0x94,0x40,0x06,0xe1] +@ CHECK: swpb r5, r1, [r9] @ encoding: [0x91,0x50,0x49,0xe1] |