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-rw-r--r--lib/Target/ARM/ARMInstrInfo.td6
-rw-r--r--lib/Target/ARM/ARMInstrNEON.td20
-rw-r--r--lib/Target/ARM/ARMInstrThumb.td2
-rw-r--r--lib/Target/ARM/ARMInstrThumb2.td2
-rw-r--r--lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp8
5 files changed, 20 insertions, 18 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index bfeddfbe50..21b42885d2 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -327,8 +327,8 @@ def addrmodepc : Operand<i32>,
let MIOperandInfo = (ops GPR, i32imm);
}
-def lane_cst : Operand<i32> {
- let PrintMethod = "printLaneOperand";
+def nohash_imm : Operand<i32> {
+ let PrintMethod = "printNoHashImmediate";
}
//===----------------------------------------------------------------------===//
@@ -581,7 +581,7 @@ def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
[]>;
def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
- (ins i32imm:$label, lane_cst:$id, pred:$p),
+ (ins i32imm:$label, nohash_imm:$id, pred:$p),
Pseudo, IIC_iALUi,
!strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
"(${label}_${id}-(",
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index 1a68dce637..4733ba0ffd 100644
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -1658,27 +1658,27 @@ def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
// VMOV : Vector Get Lane (move scalar to ARM core register)
def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
- (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
+ (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
[(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
imm:$lane))]>;
def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
- (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
+ (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
[(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
imm:$lane))]>;
def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
- (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
+ (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
[(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
imm:$lane))]>;
def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
- (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
+ (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
[(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
imm:$lane))]>;
def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
- (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
+ (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
[(set GPR:$dst, (extractelt (v2i32 DPR:$src),
imm:$lane))]>;
@@ -1715,17 +1715,17 @@ def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
let Constraints = "$src1 = $dst" in {
def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
- (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
+ (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
[(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
GPR:$src2, imm:$lane))]>;
def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
- (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
+ (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
[(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
GPR:$src2, imm:$lane))]>;
def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
- (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
+ (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
[(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
GPR:$src2, imm:$lane))]>;
@@ -1788,14 +1788,14 @@ def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
: N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
- (outs DPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
+ (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary,
!strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
[(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
ValueType ResTy, ValueType OpTy>
: N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
- (outs QPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
+ (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary,
!strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
[(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index aaff818ac5..b332042f57 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -632,7 +632,7 @@ def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
"adr$p $dst, #$label", []>;
def tLEApcrelJT : T1I<(outs tGPR:$dst),
- (ins i32imm:$label, lane_cst:$id, pred:$p),
+ (ins i32imm:$label, nohash_imm:$id, pred:$p),
IIC_iALUi, "adr$p $dst, #${label}_${id}", []>;
//===----------------------------------------------------------------------===//
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index b5b92dddc3..5dd40546bc 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -431,7 +431,7 @@ def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
"adr$p.w $dst, #$label", []>;
def t2LEApcrelJT : T2XI<(outs GPR:$dst),
- (ins i32imm:$label, lane_cst:$id, pred:$p), IIC_iALUi,
+ (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
"adr$p.w $dst, #${label}_${id}", []>;
// ADD r, sp, {so_imm|i12}
diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
index 3ef3fc5dbc..4b0f92f6ce 100644
--- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
@@ -164,7 +164,7 @@ namespace {
void printJTBlockOperand(const MachineInstr *MI, int OpNum);
void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
void printTBAddrMode(const MachineInstr *MI, int OpNum);
- void printLaneOperand(const MachineInstr *MI, int OpNum);
+ void printNoHashImmediate(const MachineInstr *MI, int OpNum);
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant, const char *ExtraCode);
@@ -1010,7 +1010,7 @@ void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
O << ']';
}
-void ARMAsmPrinter::printLaneOperand(const MachineInstr *MI, int OpNum) {
+void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
O << MI->getOperand(OpNum).getImm();
}
@@ -1029,7 +1029,9 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
}
// Fallthrough
case 'c': // Don't print "#" before an immediate operand.
- printLaneOperand(MI, OpNum);
+ if (!MI->getOperand(OpNum).isImm())
+ return true;
+ printNoHashImmediate(MI, OpNum);
return false;
case 'P': // Print a VFP double precision register.
printOperand(MI, OpNum);
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-09-18 17:48:48 +0000