diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 8 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt | 17 |
2 files changed, 21 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index eb30f79eff..65628544ff 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1331,10 +1331,10 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, let Inst{4} = 0; let Inst{3-0} = shift{3-0}; } - def rsr : AsI1<opcod, (outs GPR:$Rd), - (ins GPR:$Rn, so_reg_reg:$shift), + def rsr : AsI1<opcod, (outs GPRnopc:$Rd), + (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", - [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift, CPSR))]>, + [(set GPRnopc:$Rd, CPSR, (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, Requires<[IsARM]> { bits<4> Rd; bits<4> Rn; @@ -1368,7 +1368,7 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, cc_out:$s)>, Requires<[IsARM]>; def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"), - (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn, + (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPRnopc:$Rdn, GPRnopc:$Rdn, so_reg_reg:$shift, pred:$p, cc_out:$s)>, Requires<[IsARM]>; diff --git a/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt new file mode 100644 index 0000000000..275bae2fa2 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0x1f 0x12 0xb0 0x00 +0x1f 0x12 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0xf2 0xb0 0x00 +0x13 0xf2 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0x1f 0xb0 0x00 +0x13 0x1f 0xb0 0x00 + +# CHECK: potentially undefined +# CHECK: 0x13 0x12 0xbf 0x00 +0x13 0x12 0xbf 0x00 |