diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 13 |
2 files changed, 1 insertions, 14 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 34d7d8f6ef..03ab0d4013 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -113,7 +113,7 @@ def t_addrmode_s1 : Operand<i32>, def t_addrmode_sp : Operand<i32>, ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { let PrintMethod = "printThumbAddrModeSPOperand"; - let MIOperandInfo = (ops JustSP:$base, i32imm:$offsimm); + let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); } //===----------------------------------------------------------------------===// diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index 9fbde815cd..d393e8d7e3 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -367,19 +367,6 @@ def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], // Condition code registers. def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>; -// Just the stack pointer (for tSTRspi and friends). -def JustSP : RegisterClass<"ARM", [i32], 32, [SP]> { - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - JustSPClass::iterator - JustSPClass::allocation_order_end(const MachineFunction &MF) const { - return allocation_order_begin(MF); - } - }]; -} - //===----------------------------------------------------------------------===// // Subregister Set Definitions... now that we have all of the pieces, define the // sub registers for each register. |