diff options
| -rw-r--r-- | lib/Target/X86/InstSelectSimple.cpp | 10 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelSimple.cpp | 10 |
2 files changed, 12 insertions, 8 deletions
diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index 83987df7e2..79dbedcdc1 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -219,9 +219,12 @@ namespace { /// of the long value. /// unsigned makeAnotherReg(const Type *Ty) { + assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) && + "Current target doesn't have X86 reg info??"); + const X86RegisterInfo *MRI = + static_cast<const X86RegisterInfo*>(TM.getRegisterInfo()); if (Ty == Type::LongTy || Ty == Type::ULongTy) { - const TargetRegisterClass *RC = - TM.getRegisterInfo()->getRegClassForType(Type::IntTy); + const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy); // Create the lower part F->getSSARegMap()->createVirtualRegister(RC); // Create the upper part. @@ -229,8 +232,7 @@ namespace { } // Add the mapping of regnumber => reg class to MachineFunction - const TargetRegisterClass *RC = - TM.getRegisterInfo()->getRegClassForType(Ty); + const TargetRegisterClass *RC = MRI->getRegClassForType(Ty); return F->getSSARegMap()->createVirtualRegister(RC); } diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp index 83987df7e2..79dbedcdc1 100644 --- a/lib/Target/X86/X86ISelSimple.cpp +++ b/lib/Target/X86/X86ISelSimple.cpp @@ -219,9 +219,12 @@ namespace { /// of the long value. /// unsigned makeAnotherReg(const Type *Ty) { + assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) && + "Current target doesn't have X86 reg info??"); + const X86RegisterInfo *MRI = + static_cast<const X86RegisterInfo*>(TM.getRegisterInfo()); if (Ty == Type::LongTy || Ty == Type::ULongTy) { - const TargetRegisterClass *RC = - TM.getRegisterInfo()->getRegClassForType(Type::IntTy); + const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy); // Create the lower part F->getSSARegMap()->createVirtualRegister(RC); // Create the upper part. @@ -229,8 +232,7 @@ namespace { } // Add the mapping of regnumber => reg class to MachineFunction - const TargetRegisterClass *RC = - TM.getRegisterInfo()->getRegClassForType(Ty); + const TargetRegisterClass *RC = MRI->getRegClassForType(Ty); return F->getSSARegMap()->createVirtualRegister(RC); } |