diff options
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 7 | ||||
| -rw-r--r-- | test/CodeGen/Thumb2/sign_extend_inreg.ll | 22 |
2 files changed, 27 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index f8c17b8ac2..d8582ecf05 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -393,8 +393,11 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); - if (!Subtarget->hasV6Ops() && (!Subtarget->isThumb2() - || !Subtarget->hasT2ExtractPack())) { + // If the subtarget does not have extract instructions, sign_extend_inreg + // needs to be expanded. Extract is available in ARM mode on v6 and up, + // and on most Thumb2 implementations. + if ((!Subtarget->isThumb() && !Subtarget->hasV6Ops()) + || (Subtarget->isThumb2() && !Subtarget->hasT2ExtractPack())) { setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); } diff --git a/test/CodeGen/Thumb2/sign_extend_inreg.ll b/test/CodeGen/Thumb2/sign_extend_inreg.ll new file mode 100644 index 0000000000..9a02c1caeb --- /dev/null +++ b/test/CodeGen/Thumb2/sign_extend_inreg.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-A8 +; RUN: llc < %s -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK-M3 + +target triple = "thumbv7-apple-darwin10" + +define arm_apcscc i32 @f1(i16* %ptr) nounwind { +; CHECK-A8: f1 +; CHECK-A8: sxth +; CHECK-M3: f1 +; CHECK-M3-NOT: sxth +; CHECK-M3: bx lr + %1 = load i16* %ptr + %2 = icmp eq i16 %1, 1 + %3 = sext i16 %1 to i32 + br i1 %2, label %.next, label %.exit + +.next: + br label %.exit + +.exit: + ret i32 %3 +} |