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-rw-r--r--include/llvm/CodeGen/Passes.h2
-rw-r--r--lib/CodeGen/Passes.cpp42
-rw-r--r--lib/Target/ARM/ARMTargetMachine.cpp20
-rw-r--r--lib/Target/CellSPU/SPUTargetMachine.cpp6
-rw-r--r--lib/Target/Hexagon/HexagonTargetMachine.cpp16
-rw-r--r--lib/Target/MBlaze/MBlazeTargetMachine.cpp4
-rw-r--r--lib/Target/MSP430/MSP430TargetMachine.cpp4
-rw-r--r--lib/Target/Mips/MipsTargetMachine.cpp14
-rw-r--r--lib/Target/PTX/PTXTargetMachine.cpp8
-rw-r--r--lib/Target/PowerPC/PPCTargetMachine.cpp4
-rw-r--r--lib/Target/Sparc/SparcTargetMachine.cpp6
-rw-r--r--lib/Target/X86/X86TargetMachine.cpp12
-rw-r--r--lib/Target/XCore/XCoreTargetMachine.cpp2
13 files changed, 69 insertions, 71 deletions
diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h
index 3b38199858..e76fe99257 100644
--- a/include/llvm/CodeGen/Passes.h
+++ b/include/llvm/CodeGen/Passes.h
@@ -56,7 +56,7 @@ public:
protected:
TargetMachine *TM;
- PassManagerBase ±
+ PassManagerBase *PM;
PassConfigImpl *Impl; // Internal data structures
bool Initialized; // Flagged after all passes are configured.
diff --git a/lib/CodeGen/Passes.cpp b/lib/CodeGen/Passes.cpp
index 13d1bbc310..490547bbb8 100644
--- a/lib/CodeGen/Passes.cpp
+++ b/lib/CodeGen/Passes.cpp
@@ -207,7 +207,7 @@ TargetPassConfig::~TargetPassConfig() {
// Out of line constructor provides default values for pass options and
// registers all common codegen passes.
TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
- : ImmutablePass(ID), TM(tm), PM(pm), Impl(0), Initialized(false),
+ : ImmutablePass(ID), TM(tm), PM(&pm), Impl(0), Initialized(false),
DisableVerify(false),
EnableTailMerge(true) {
@@ -234,7 +234,7 @@ TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
}
TargetPassConfig::TargetPassConfig()
- : ImmutablePass(ID), PM(*(PassManagerBase*)0) {
+ : ImmutablePass(ID), PM(0) {
llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
}
@@ -269,16 +269,16 @@ AnalysisID TargetPassConfig::addPass(char &ID) {
Pass *P = Pass::createPass(FinalID);
if (!P)
llvm_unreachable("Pass ID not registered");
- PM.add(P);
+ PM->add(P);
return FinalID;
}
void TargetPassConfig::printAndVerify(const char *Banner) const {
if (TM->shouldPrintMachineCode())
- PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
+ PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
if (VerifyMachineCode)
- PM.add(createMachineVerifierPass(Banner));
+ PM->add(createMachineVerifierPass(Banner));
}
/// Add common target configurable passes that perform LLVM IR to IR transforms
@@ -288,46 +288,46 @@ void TargetPassConfig::addIRPasses() {
// Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
// BasicAliasAnalysis wins if they disagree. This is intended to help
// support "obvious" type-punning idioms.
- PM.add(createTypeBasedAliasAnalysisPass());
- PM.add(createBasicAliasAnalysisPass());
+ PM->add(createTypeBasedAliasAnalysisPass());
+ PM->add(createBasicAliasAnalysisPass());
// Before running any passes, run the verifier to determine if the input
// coming from the front-end and/or optimizer is valid.
if (!DisableVerify)
- PM.add(createVerifierPass());
+ PM->add(createVerifierPass());
// Run loop strength reduction before anything else.
if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
- PM.add(createLoopStrengthReducePass(getTargetLowering()));
+ PM->add(createLoopStrengthReducePass(getTargetLowering()));
if (PrintLSR)
- PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
+ PM->add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
}
- PM.add(createGCLoweringPass());
+ PM->add(createGCLoweringPass());
// Make sure that no unreachable blocks are instruction selected.
- PM.add(createUnreachableBlockEliminationPass());
+ PM->add(createUnreachableBlockEliminationPass());
}
/// Add common passes that perform LLVM IR to IR transforms in preparation for
/// instruction selection.
void TargetPassConfig::addISelPrepare() {
if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
- PM.add(createCodeGenPreparePass(getTargetLowering()));
+ PM->add(createCodeGenPreparePass(getTargetLowering()));
- PM.add(createStackProtectorPass(getTargetLowering()));
+ PM->add(createStackProtectorPass(getTargetLowering()));
addPreISel();
if (PrintISelInput)
- PM.add(createPrintFunctionPass("\n\n"
- "*** Final LLVM Code input to ISel ***\n",
- &dbgs()));
+ PM->add(createPrintFunctionPass("\n\n"
+ "*** Final LLVM Code input to ISel ***\n",
+ &dbgs()));
// All passes which modify the LLVM IR are now complete; run the verifier
// to ensure that the IR is valid.
if (!DisableVerify)
- PM.add(createVerifierPass());
+ PM->add(createVerifierPass());
}
/// Add the complete set of target-independent postISel code generator passes.
@@ -405,7 +405,7 @@ void TargetPassConfig::addMachinePasses() {
// GC
addPass(GCMachineCodeAnalysisID);
if (PrintGCInfo)
- PM.add(createGCInfoPrinter(dbgs()));
+ PM->add(createGCInfoPrinter(dbgs()));
// Basic block placement.
if (getOptLevel() != CodeGenOpt::None)
@@ -522,7 +522,7 @@ void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
addPass(PHIEliminationID);
addPass(TwoAddressInstructionPassID);
- PM.add(RegAllocPass);
+ PM->add(RegAllocPass);
printAndVerify("After Register Allocation");
}
@@ -564,7 +564,7 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
printAndVerify("After Machine Scheduling");
// Add the selected register allocation pass.
- PM.add(RegAllocPass);
+ PM->add(RegAllocPass);
printAndVerify("After Register Allocation");
// FinalizeRegAlloc is convenient until MachineInstrBundles is more mature,
diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index 047efc23a4..9aa8308920 100644
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -136,22 +136,22 @@ TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
bool ARMPassConfig::addPreISel() {
if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
- PM.add(createGlobalMergePass(TM->getTargetLowering()));
+ PM->add(createGlobalMergePass(TM->getTargetLowering()));
return false;
}
bool ARMPassConfig::addInstSelector() {
- PM.add(createARMISelDag(getARMTargetMachine(), getOptLevel()));
+ PM->add(createARMISelDag(getARMTargetMachine(), getOptLevel()));
return false;
}
bool ARMPassConfig::addPreRegAlloc() {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
- PM.add(createARMLoadStoreOptimizationPass(true));
+ PM->add(createARMLoadStoreOptimizationPass(true));
if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
- PM.add(createMLxExpansionPass());
+ PM->add(createMLxExpansionPass());
return true;
}
@@ -159,23 +159,23 @@ bool ARMPassConfig::addPreSched2() {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (getOptLevel() != CodeGenOpt::None) {
if (!getARMSubtarget().isThumb1Only()) {
- PM.add(createARMLoadStoreOptimizationPass());
+ PM->add(createARMLoadStoreOptimizationPass());
printAndVerify("After ARM load / store optimizer");
}
if (getARMSubtarget().hasNEON())
- PM.add(createExecutionDependencyFixPass(&ARM::DPRRegClass));
+ PM->add(createExecutionDependencyFixPass(&ARM::DPRRegClass));
}
// Expand some pseudo instructions into multiple instructions to allow
// proper scheduling.
- PM.add(createARMExpandPseudoPass());
+ PM->add(createARMExpandPseudoPass());
if (getOptLevel() != CodeGenOpt::None) {
if (!getARMSubtarget().isThumb1Only())
addPass(IfConverterID);
}
if (getARMSubtarget().isThumb2())
- PM.add(createThumb2ITBlockPass());
+ PM->add(createThumb2ITBlockPass());
return true;
}
@@ -183,13 +183,13 @@ bool ARMPassConfig::addPreSched2() {
bool ARMPassConfig::addPreEmitPass() {
if (getARMSubtarget().isThumb2()) {
if (!getARMSubtarget().prefers32BitThumb())
- PM.add(createThumb2SizeReductionPass());
+ PM->add(createThumb2SizeReductionPass());
// Constant island pass work on unbundled instructions.
addPass(UnpackMachineBundlesID);
}
- PM.add(createARMConstantIslandPass());
+ PM->add(createARMConstantIslandPass());
return true;
}
diff --git a/lib/Target/CellSPU/SPUTargetMachine.cpp b/lib/Target/CellSPU/SPUTargetMachine.cpp
index 21f6b25bf2..3b90261fe6 100644
--- a/lib/Target/CellSPU/SPUTargetMachine.cpp
+++ b/lib/Target/CellSPU/SPUTargetMachine.cpp
@@ -72,7 +72,7 @@ TargetPassConfig *SPUTargetMachine::createPassConfig(PassManagerBase &PM) {
bool SPUPassConfig::addInstSelector() {
// Install an instruction selector.
- PM.add(createSPUISelDag(getSPUTargetMachine()));
+ PM->add(createSPUISelDag(getSPUTargetMachine()));
return false;
}
@@ -85,9 +85,9 @@ bool SPUPassConfig::addPreEmitPass() {
(BuilderFunc)(intptr_t)sys::DynamicLibrary::SearchForAddressOfSymbol(
"createTCESchedulerPass");
if (schedulerCreator != NULL)
- PM.add(schedulerCreator("cellspu"));
+ PM->add(schedulerCreator("cellspu"));
//align instructions with nops/lnops for dual issue
- PM.add(createSPUNopFillerPass(getSPUTargetMachine()));
+ PM->add(createSPUNopFillerPass(getSPUTargetMachine()));
return true;
}
diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp
index b9e6894936..55bbba7251 100644
--- a/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -100,23 +100,23 @@ TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
}
bool HexagonPassConfig::addInstSelector() {
- PM.add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
- PM.add(createHexagonISelDag(getHexagonTargetMachine()));
- PM.add(createHexagonPeephole());
+ PM->add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
+ PM->add(createHexagonISelDag(getHexagonTargetMachine()));
+ PM->add(createHexagonPeephole());
return false;
}
bool HexagonPassConfig::addPreRegAlloc() {
if (!DisableHardwareLoops) {
- PM.add(createHexagonHardwareLoops());
+ PM->add(createHexagonHardwareLoops());
}
return false;
}
bool HexagonPassConfig::addPostRegAlloc() {
- PM.add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
+ PM->add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
return true;
}
@@ -129,14 +129,14 @@ bool HexagonPassConfig::addPreSched2() {
bool HexagonPassConfig::addPreEmitPass() {
if (!DisableHardwareLoops) {
- PM.add(createHexagonFixupHwLoops());
+ PM->add(createHexagonFixupHwLoops());
}
// Expand Spill code for predicate registers.
- PM.add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
+ PM->add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
// Split up TFRcondsets into conditional transfers.
- PM.add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
+ PM->add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
return false;
}
diff --git a/lib/Target/MBlaze/MBlazeTargetMachine.cpp b/lib/Target/MBlaze/MBlazeTargetMachine.cpp
index dd7de9bff3..62393d0920 100644
--- a/lib/Target/MBlaze/MBlazeTargetMachine.cpp
+++ b/lib/Target/MBlaze/MBlazeTargetMachine.cpp
@@ -68,7 +68,7 @@ TargetPassConfig *MBlazeTargetMachine::createPassConfig(PassManagerBase &PM) {
// Install an instruction selector pass using
// the ISelDag to gen MBlaze code.
bool MBlazePassConfig::addInstSelector() {
- PM.add(createMBlazeISelDag(getMBlazeTargetMachine()));
+ PM->add(createMBlazeISelDag(getMBlazeTargetMachine()));
return false;
}
@@ -76,6 +76,6 @@ bool MBlazePassConfig::addInstSelector() {
// machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes.
bool MBlazePassConfig::addPreEmitPass() {
- PM.add(createMBlazeDelaySlotFillerPass(getMBlazeTargetMachine()));
+ PM->add(createMBlazeDelaySlotFillerPass(getMBlazeTargetMachine()));
return true;
}
diff --git a/lib/Target/MSP430/MSP430TargetMachine.cpp b/lib/Target/MSP430/MSP430TargetMachine.cpp
index 9f2eda13d7..3acf96bb7d 100644
--- a/lib/Target/MSP430/MSP430TargetMachine.cpp
+++ b/lib/Target/MSP430/MSP430TargetMachine.cpp
@@ -60,12 +60,12 @@ TargetPassConfig *MSP430TargetMachine::createPassConfig(PassManagerBase &PM) {
bool MSP430PassConfig::addInstSelector() {
// Install an instruction selector.
- PM.add(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
+ PM->add(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
return false;
}
bool MSP430PassConfig::addPreEmitPass() {
// Must run branch selection immediately preceding the asm printer.
- PM.add(createMSP430BranchSelectionPass());
+ PM->add(createMSP430BranchSelectionPass());
return false;
}
diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp
index ad022311ed..858723bad9 100644
--- a/lib/Target/Mips/MipsTargetMachine.cpp
+++ b/lib/Target/Mips/MipsTargetMachine.cpp
@@ -117,18 +117,16 @@ TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
// Install an instruction selector pass using
// the ISelDag to gen Mips code.
-bool MipsPassConfig::addInstSelector()
-{
- PM.add(createMipsISelDag(getMipsTargetMachine()));
+bool MipsPassConfig::addInstSelector() {
+ PM->add(createMipsISelDag(getMipsTargetMachine()));
return false;
}
// Implemented by targets that want to run passes immediately before
// machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes.
-bool MipsPassConfig::addPreEmitPass()
-{
- PM.add(createMipsDelaySlotFillerPass(getMipsTargetMachine()));
+bool MipsPassConfig::addPreEmitPass() {
+ PM->add(createMipsDelaySlotFillerPass(getMipsTargetMachine()));
return true;
}
@@ -136,12 +134,12 @@ bool MipsPassConfig::addPreRegAlloc() {
// Do not restore $gp if target is Mips64.
// In N32/64, $gp is a callee-saved register.
if (!getMipsSubtarget().hasMips64())
- PM.add(createMipsEmitGPRestorePass(getMipsTargetMachine()));
+ PM->add(createMipsEmitGPRestorePass(getMipsTargetMachine()));
return true;
}
bool MipsPassConfig::addPreSched2() {
- PM.add(createMipsExpandPseudoPass(getMipsTargetMachine()));
+ PM->add(createMipsExpandPseudoPass(getMipsTargetMachine()));
return true;
}
diff --git a/lib/Target/PTX/PTXTargetMachine.cpp b/lib/Target/PTX/PTXTargetMachine.cpp
index c55a658dc3..97b8de1a0b 100644
--- a/lib/Target/PTX/PTXTargetMachine.cpp
+++ b/lib/Target/PTX/PTXTargetMachine.cpp
@@ -130,7 +130,7 @@ TargetPassConfig *PTXTargetMachine::createPassConfig(PassManagerBase &PM) {
}
bool PTXPassConfig::addInstSelector() {
- PM.add(createPTXISelDag(getPTXTargetMachine(), getOptLevel()));
+ PM->add(createPTXISelDag(getPTXTargetMachine(), getOptLevel()));
return false;
}
@@ -145,7 +145,7 @@ void PTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
bool PTXPassConfig::addPostRegAlloc() {
// PTXMFInfoExtract must after register allocation!
- //PM.add(createPTXMFInfoExtract(getPTXTargetMachine()));
+ //PM->add(createPTXMFInfoExtract(getPTXTargetMachine()));
return false;
}
@@ -159,7 +159,7 @@ void PTXPassConfig::addMachineLateOptimization() {
}
bool PTXPassConfig::addPreEmitPass() {
- PM.add(createPTXMFInfoExtract(getPTXTargetMachine(), getOptLevel()));
- PM.add(createPTXFPRoundingModePass(getPTXTargetMachine(), getOptLevel()));
+ PM->add(createPTXMFInfoExtract(getPTXTargetMachine(), getOptLevel()));
+ PM->add(createPTXFPRoundingModePass(getPTXTargetMachine(), getOptLevel()));
return true;
}
diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index d113976699..50f3db8b27 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -98,13 +98,13 @@ TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
bool PPCPassConfig::addInstSelector() {
// Install an instruction selector.
- PM.add(createPPCISelDag(getPPCTargetMachine()));
+ PM->add(createPPCISelDag(getPPCTargetMachine()));
return false;
}
bool PPCPassConfig::addPreEmitPass() {
// Must run branch selection immediately preceding the asm printer.
- PM.add(createPPCBranchSelectionPass());
+ PM->add(createPPCBranchSelectionPass());
return false;
}
diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp
index 6f313562c1..cc253077a9 100644
--- a/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -59,7 +59,7 @@ TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
}
bool SparcPassConfig::addInstSelector() {
- PM.add(createSparcISelDag(getSparcTargetMachine()));
+ PM->add(createSparcISelDag(getSparcTargetMachine()));
return false;
}
@@ -67,8 +67,8 @@ bool SparcPassConfig::addInstSelector() {
/// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes.
bool SparcPassConfig::addPreEmitPass(){
- PM.add(createSparcFPMoverPass(getSparcTargetMachine()));
- PM.add(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
+ PM->add(createSparcFPMoverPass(getSparcTargetMachine()));
+ PM->add(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
return true;
}
diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index f4b7a6277a..89c388415b 100644
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -145,34 +145,34 @@ TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
bool X86PassConfig::addInstSelector() {
// Install an instruction selector.
- PM.add(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
+ PM->add(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
// For 32-bit, prepend instructions to set the "global base reg" for PIC.
if (!getX86Subtarget().is64Bit())
- PM.add(createGlobalBaseRegPass());
+ PM->add(createGlobalBaseRegPass());
return false;
}
bool X86PassConfig::addPreRegAlloc() {
- PM.add(createX86MaxStackAlignmentHeuristicPass());
+ PM->add(createX86MaxStackAlignmentHeuristicPass());
return false; // -print-machineinstr shouldn't print after this.
}
bool X86PassConfig::addPostRegAlloc() {
- PM.add(createX86FloatingPointStackifierPass());
+ PM->add(createX86FloatingPointStackifierPass());
return true; // -print-machineinstr should print after this.
}
bool X86PassConfig::addPreEmitPass() {
bool ShouldPrint = false;
if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
- PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
+ PM->add(createExecutionDependencyFixPass(&X86::VR128RegClass));
ShouldPrint = true;
}
if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
- PM.add(createX86IssueVZeroUpperPass());
+ PM->add(createX86IssueVZeroUpperPass());
ShouldPrint = true;
}
diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp
index f65297e54a..5afd5a1aff 100644
--- a/lib/Target/XCore/XCoreTargetMachine.cpp
+++ b/lib/Target/XCore/XCoreTargetMachine.cpp
@@ -55,7 +55,7 @@ TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
}
bool XCorePassConfig::addInstSelector() {
- PM.add(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
+ PM->add(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
return false;
}
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-11-21 16:33:38 +0000