diff options
| -rw-r--r-- | lib/CodeGen/SimpleRegisterCoalescing.cpp | 16 | ||||
| -rw-r--r-- | test/CodeGen/X86/2009-03-11-CoalescerBug.ll | 85 |
2 files changed, 96 insertions, 5 deletions
diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index c29ee62c83..277b1e6d27 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -400,9 +400,6 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx); BHasPHIKill |= DLR->valno->hasPHIKill; assert(DLR->valno->def == DefIdx); - if (BHasSubRegs) - // Don't know how to update sub-register live intervals. - return false; BDeadValNos.push_back(DLR->valno); BExtend[DLR->start] = DLR->end; JoinedCopies.insert(UseMI); @@ -418,8 +415,17 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, DOUT << "\nExtending: "; IntB.print(DOUT, tri_); // Remove val#'s defined by copies that will be coalesced away. - for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) + for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) { + VNInfo *DeadVNI = BDeadValNos[i]; + if (BHasSubRegs) { + for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) { + LiveInterval &SRLI = li_->getInterval(*SR); + const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def); + SRLI.removeValNo(SRLR->valno); + } + } IntB.removeValNo(BDeadValNos[i]); + } // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition // is updated. Kills are also updated. @@ -443,7 +449,7 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, // If the IntB live range is assigned to a physical register, and if that // physreg has sub-registers, update their live intervals as well. - if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) { + if (BHasSubRegs) { for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) { LiveInterval &SRLI = li_->getInterval(*SR); SRLI.MergeInClobberRange(AI->start, End, li_->getVNInfoAllocator()); diff --git a/test/CodeGen/X86/2009-03-11-CoalescerBug.ll b/test/CodeGen/X86/2009-03-11-CoalescerBug.ll new file mode 100644 index 0000000000..1f5631764b --- /dev/null +++ b/test/CodeGen/X86/2009-03-11-CoalescerBug.ll @@ -0,0 +1,85 @@ +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin9 -stats |& grep regcoalescing | grep commuting + +@lookupTable5B = external global [64 x i32], align 32 ; <[64 x i32]*> [#uses=1] +@lookupTable3B = external global [16 x i32], align 32 ; <[16 x i32]*> [#uses=1] +@disparity0 = external global i32 ; <i32*> [#uses=5] +@disparity1 = external global i32 ; <i32*> [#uses=3] + +define i32 @calc(i32 %theWord, i32 %k) nounwind { +entry: + %0 = lshr i32 %theWord, 3 ; <i32> [#uses=1] + %1 = and i32 %0, 31 ; <i32> [#uses=1] + %2 = shl i32 %k, 5 ; <i32> [#uses=1] + %3 = or i32 %1, %2 ; <i32> [#uses=1] + %4 = and i32 %theWord, 7 ; <i32> [#uses=1] + %5 = shl i32 %k, 3 ; <i32> [#uses=1] + %6 = or i32 %5, %4 ; <i32> [#uses=1] + %7 = getelementptr [64 x i32]* @lookupTable5B, i32 0, i32 %3 ; <i32*> [#uses=1] + %8 = load i32* %7, align 4 ; <i32> [#uses=5] + %9 = getelementptr [16 x i32]* @lookupTable3B, i32 0, i32 %6 ; <i32*> [#uses=1] + %10 = load i32* %9, align 4 ; <i32> [#uses=5] + %11 = and i32 %8, 65536 ; <i32> [#uses=1] + %12 = icmp eq i32 %11, 0 ; <i1> [#uses=1] + br i1 %12, label %bb1, label %bb + +bb: ; preds = %entry + %13 = and i32 %8, 994 ; <i32> [#uses=1] + %14 = load i32* @disparity0, align 4 ; <i32> [#uses=2] + store i32 %14, i32* @disparity1, align 4 + br label %bb8 + +bb1: ; preds = %entry + %15 = lshr i32 %8, 18 ; <i32> [#uses=1] + %16 = and i32 %15, 1 ; <i32> [#uses=1] + %17 = load i32* @disparity0, align 4 ; <i32> [#uses=4] + %18 = icmp eq i32 %16, %17 ; <i1> [#uses=1] + %not = select i1 %18, i32 0, i32 994 ; <i32> [#uses=1] + %.masked = and i32 %8, 994 ; <i32> [#uses=1] + %result.1 = xor i32 %not, %.masked ; <i32> [#uses=2] + %19 = and i32 %8, 524288 ; <i32> [#uses=1] + %20 = icmp eq i32 %19, 0 ; <i1> [#uses=1] + br i1 %20, label %bb7, label %bb6 + +bb6: ; preds = %bb1 + %21 = xor i32 %17, 1 ; <i32> [#uses=2] + store i32 %21, i32* @disparity1, align 4 + br label %bb8 + +bb7: ; preds = %bb1 + store i32 %17, i32* @disparity1, align 4 + br label %bb8 + +bb8: ; preds = %bb7, %bb6, %bb + %22 = phi i32 [ %17, %bb7 ], [ %21, %bb6 ], [ %14, %bb ] ; <i32> [#uses=4] + %result.0 = phi i32 [ %result.1, %bb7 ], [ %result.1, %bb6 ], [ %13, %bb ] ; <i32> [#uses=2] + %23 = and i32 %10, 65536 ; <i32> [#uses=1] + %24 = icmp eq i32 %23, 0 ; <i1> [#uses=1] + br i1 %24, label %bb10, label %bb9 + +bb9: ; preds = %bb8 + %25 = and i32 %10, 29 ; <i32> [#uses=1] + %26 = or i32 %result.0, %25 ; <i32> [#uses=1] + store i32 %22, i32* @disparity0, align 4 + ret i32 %26 + +bb10: ; preds = %bb8 + %27 = lshr i32 %10, 18 ; <i32> [#uses=1] + %28 = and i32 %27, 1 ; <i32> [#uses=1] + %29 = icmp eq i32 %28, %22 ; <i1> [#uses=1] + %not13 = select i1 %29, i32 0, i32 29 ; <i32> [#uses=1] + %.masked20 = and i32 %10, 29 ; <i32> [#uses=1] + %.pn = xor i32 %not13, %.masked20 ; <i32> [#uses=1] + %result.3 = or i32 %.pn, %result.0 ; <i32> [#uses=2] + %30 = and i32 %10, 524288 ; <i32> [#uses=1] + %31 = icmp eq i32 %30, 0 ; <i1> [#uses=1] + br i1 %31, label %bb17, label %bb16 + +bb16: ; preds = %bb10 + %32 = xor i32 %22, 1 ; <i32> [#uses=1] + store i32 %32, i32* @disparity0, align 4 + ret i32 %result.3 + +bb17: ; preds = %bb10 + store i32 %22, i32* @disparity0, align 4 + ret i32 %result.3 +} |