diff options
| -rw-r--r-- | lib/Target/CellSPU/SPUISelLowering.cpp | 9 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/sext128.ll | 3 |
2 files changed, 10 insertions, 2 deletions
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 38b9f4e523..2a82988ce0 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -2642,11 +2642,16 @@ static SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) DAG.getNode(SPUISD::PREFSLOT2VEC, dl, mvt, Op0, Op0), DAG.getConstant(31, MVT::i32)); + // reinterpret as a i128 (SHUFB requires it). This gets lowered away. + SDValue extended = SDValue(DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, + dl, Op0VT, Op0, + DAG.getTargetConstant( + SPU::GPRCRegClass.getID(), + MVT::i32)), 0); // Shuffle bytes - Copy the sign bits into the upper 64 bits // and the input value into the lower 64 bits. SDValue extShuffle = DAG.getNode(SPUISD::SHUFB, dl, mvt, - DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i128, Op0), sraVal, shufMask); - + extended, sraVal, shufMask); return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, extShuffle); } diff --git a/test/CodeGen/CellSPU/sext128.ll b/test/CodeGen/CellSPU/sext128.ll index 0c0b3599b1..8a5b609d79 100644 --- a/test/CodeGen/CellSPU/sext128.ll +++ b/test/CodeGen/CellSPU/sext128.ll @@ -12,6 +12,7 @@ entry: ; CHECK: long 269488144 ; CHECK: long 66051 ; CHECK: long 67438087 +; CHECK-NOT: rotqmbyi ; CHECK: rotmai ; CHECK: lqa ; CHECK: shufb @@ -25,6 +26,7 @@ entry: ; CHECK: long 269488144 ; CHECK: long 269488144 ; CHECK: long 66051 +; CHECK-NOT: rotqmbyi ; CHECK: rotmai ; CHECK: lqa ; CHECK: shufb @@ -39,6 +41,7 @@ entry: ; CHECK: long 269488144 ; CHECK: long 269488144 ; CHECK: long 66051 +; CHECK-NOT: rotqmbyi ; CHECK: rotmai ; CHECK: lqa ; CHECK: shufb |