diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 637 |
1 files changed, 330 insertions, 307 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 4c49724bb7..47450eab93 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -287,7 +287,7 @@ private: SDValue &Hi); SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl); - SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT); + SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl); SDValue ExpandBUILD_VECTOR(SDNode *Node); SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, @@ -299,12 +299,12 @@ private: SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned, DebugLoc dl); - SDValue ExpandBSWAP(SDValue Op); - SDValue ExpandBitCount(unsigned Opc, SDValue Op); + SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); + SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt, - SDValue &Lo, SDValue &Hi); + SDValue &Lo, SDValue &Hi, DebugLoc dl); void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt, - SDValue &Lo, SDValue &Hi); + SDValue &Lo, SDValue &Hi, DebugLoc dl); SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op); SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op); @@ -3725,7 +3725,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { break; } case TargetLowering::Expand: - Result = ExpandBSWAP(Tmp1); + Result = ExpandBSWAP(Tmp1, dl); break; } break; @@ -3776,7 +3776,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { break; } case TargetLowering::Expand: - Result = ExpandBitCount(Node->getOpcode(), Tmp1); + Result = ExpandBitCount(Node->getOpcode(), Tmp1, dl); break; } break; @@ -3933,7 +3933,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { case ISD::BIT_CONVERT: if (!isTypeLegal(Node->getOperand(0).getValueType())) { Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), - Node->getValueType(0)); + Node->getValueType(0), dl); } else if (Op.getOperand(0).getValueType().isVector()) { // The input has to be a vector type, we have to either scalarize it, pack // it, or convert it based on whether the input vector type is legal. @@ -3965,7 +3965,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { default: assert(0 && "Unknown operation action!"); case TargetLowering::Expand: Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), - Node->getValueType(0)); + Node->getValueType(0), dl); break; case TargetLowering::Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); @@ -4163,7 +4163,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { // The only other way we can lower this is to turn it into a STORE, // LOAD pair, targetting a temporary location (a stack slot). - Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); + Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT, dl); break; } switch (getTypeAction(Node->getOperand(0).getValueType())) { @@ -4193,7 +4193,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { } // The only other way we can lower this is to turn it into a STORE, // LOAD pair, targetting a temporary location (a stack slot). - Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); + Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT, dl); break; } switch (getTypeAction(Node->getOperand(0).getValueType())) { @@ -4278,7 +4278,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { // slots and always reusing the same one. We currently always create // new ones, as reuse may inhibit scheduling. Result = EmitStackConvert(Node->getOperand(0), ExtraVT, - Node->getValueType(0)); + Node->getValueType(0), dl); } else { assert(0 && "Unknown op"); } @@ -4483,6 +4483,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { SDValue Tmp1, Tmp2, Tmp3; SDValue Result; SDNode *Node = Op.getNode(); + DebugLoc dl = Node->getDebugLoc(); DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op); if (I != PromotedNodes.end()) return I->second; @@ -4497,17 +4498,17 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { assert(0 && "Do not know how to promote this operator!"); abort(); case ISD::UNDEF: - Result = DAG.getNode(ISD::UNDEF, NVT); + Result = DAG.getNode(ISD::UNDEF, dl, NVT); break; case ISD::Constant: if (VT != MVT::i1) - Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); + Result = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Op); else - Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); + Result = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Op); assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); break; case ISD::ConstantFP: - Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); + Result = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op); assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); break; @@ -4515,7 +4516,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { MVT VT0 = Node->getOperand(0).getValueType(); assert(isTypeLegal(TLI.getSetCCResultType(VT0)) && "SetCC type is not legal??"); - Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(VT0), + Result = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(VT0), Node->getOperand(0), Node->getOperand(1), Node->getOperand(2)); break; @@ -4527,7 +4528,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { assert(Result.getValueType().bitsGE(NVT) && "This truncation doesn't make sense!"); if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT - Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); + Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Result); break; case Promote: // The truncation is not required, because we don't guarantee anything @@ -4537,7 +4538,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { case Expand: ExpandOp(Node->getOperand(0), Tmp1, Tmp2); // Truncate the low part of the expanded value to the result type - Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); + Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Tmp1); } break; case ISD::SIGN_EXTEND: @@ -4547,17 +4548,17 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); case Legal: // Input is legal? Just do extend all the way to the larger type. - Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0)); break; case Promote: // Promote the reg if it's smaller. Result = PromoteOp(Node->getOperand(0)); // The high bits are not guaranteed to be anything. Insert an extend. if (Node->getOpcode() == ISD::SIGN_EXTEND) - Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, + Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result, DAG.getValueType(Node->getOperand(0).getValueType())); else if (Node->getOpcode() == ISD::ZERO_EXTEND) - Result = DAG.getZeroExtendInReg(Result, + Result = DAG.getZeroExtendInReg(Result, dl, Node->getOperand(0).getValueType()); break; } @@ -4577,7 +4578,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { } case ISD::BIT_CONVERT: Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), - Node->getValueType(0)); + Node->getValueType(0), dl); Result = PromoteOp(Result); break; @@ -4590,11 +4591,11 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { case Legal: if (Node->getConstantOperandVal(1) == 0) { // Input is legal? Do an FP_ROUND_INREG. - Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), + Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Node->getOperand(0), DAG.getValueType(VT)); } else { // Just remove the truncate, it isn't affecting the value. - Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), + Result = DAG.getNode(ISD::FP_ROUND, dl, NVT, Node->getOperand(0), Node->getOperand(1)); } break; @@ -4605,27 +4606,27 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { switch (getTypeAction(Node->getOperand(0).getValueType())) { case Legal: // No extra round required here. - Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0)); break; case Promote: Result = PromoteOp(Node->getOperand(0)); if (Node->getOpcode() == ISD::SINT_TO_FP) - Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), + Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(), Result, DAG.getValueType(Node->getOperand(0).getValueType())); else - Result = DAG.getZeroExtendInReg(Result, + Result = DAG.getZeroExtendInReg(Result, dl, Node->getOperand(0).getValueType()); // No extra round required here. - Result = DAG.getNode(Node->getOpcode(), NVT, Result); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Result); break; case Expand: Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, - Node->getOperand(0), Node->getDebugLoc()); + Node->getOperand(0), dl); // Round if we cannot tolerate excess precision. if (NoExcessFPPrecision) - Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, + Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, DAG.getValueType(VT)); break; } @@ -4633,7 +4634,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { case ISD::SIGN_EXTEND_INREG: Result = PromoteOp(Node->getOperand(0)); - Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, + Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result, Node->getOperand(1)); break; case ISD::FP_TO_SINT: @@ -4658,9 +4659,9 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) && (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) || TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ - Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); + Result = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Tmp1); } else { - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); } break; @@ -4668,7 +4669,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { case ISD::FNEG: Tmp1 = PromoteOp(Node->getOperand(0)); assert(Tmp1.getValueType() == NVT); - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); // NOTE: we do not have to do any extra rounding here for // NoExcessFPPrecision, because we know the input will have the appropriate // precision, and these operations don't modify precision at all. @@ -4689,9 +4690,9 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { case ISD::FNEARBYINT: Tmp1 = PromoteOp(Node->getOperand(0)); assert(Tmp1.getValueType() == NVT); - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); if (NoExcessFPPrecision) - Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, + Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, DAG.getValueType(VT)); break; @@ -4704,9 +4705,9 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { if (Node->getOpcode() == ISD::FPOW) Tmp2 = PromoteOp(Tmp2); assert(Tmp1.getValueType() == NVT); - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); if (NoExcessFPPrecision) - Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, + Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, DAG.getValueType(VT)); break; } @@ -4715,7 +4716,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); Tmp2 = PromoteOp(Node->getOperand(2)); Tmp3 = PromoteOp(Node->getOperand(3)); - Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getMemoryVT(), + Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(), AtomNode->getChain(), AtomNode->getBasePtr(), Tmp2, Tmp3, AtomNode->getSrcValue(), @@ -4737,7 +4738,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { case ISD::ATOMIC_SWAP: { AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); Tmp2 = PromoteOp(Node->getOperand(2)); - Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getMemoryVT(), + Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(), AtomNode->getChain(), AtomNode->getBasePtr(), Tmp2, AtomNode->getSrcValue(), @@ -4759,7 +4760,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { Tmp1 = PromoteOp(Node->getOperand(0)); Tmp2 = PromoteOp(Node->getOperand(1)); assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); break; case ISD::FADD: case ISD::FSUB: @@ -4767,7 +4768,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { Tmp1 = PromoteOp(Node->getOperand(0)); Tmp2 = PromoteOp(Node->getOperand(1)); assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); // Floating point operations will give excess precision that we may not be // able to tolerate. If we DO allow excess precision, just leave it, @@ -4775,7 +4776,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { // FIXME: Why would we need to round FP ops more than integer ones? // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) if (NoExcessFPPrecision) - Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, + Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, DAG.getValueType(VT)); break; @@ -4785,16 +4786,16 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { Tmp1 = PromoteOp(Node->getOperand(0)); Tmp2 = PromoteOp(Node->getOperand(1)); if (NVT.isInteger()) { - Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, + Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1, DAG.getValueType(VT)); - Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, + Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2, DAG.getValueType(VT)); } - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); // Perform FP_ROUND: this is probably overly pessimistic. if (NVT.isFloatingPoint() && NoExcessFPPrecision) - Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, + Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, DAG.getValueType(VT)); break; case ISD::FDIV: @@ -4811,11 +4812,11 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; } - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); // Perform FP_ROUND: this is probably overly pessimistic. if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) - Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, + Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, DAG.getValueType(VT)); break; @@ -4825,27 +4826,27 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { Tmp1 = PromoteOp(Node->getOperand(0)); Tmp2 = PromoteOp(Node->getOperand(1)); assert(NVT.isInteger() && "Operators don't apply to FP!"); - Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); - Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); - Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); + Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT); + Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT); + Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); break; case ISD::SHL: Tmp1 = PromoteOp(Node->getOperand(0)); - Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); + Result = DAG.getNode(ISD::SHL, dl, NVT, Tmp1, Node->getOperand(1)); break; case ISD::SRA: // The input value must be properly sign extended. Tmp1 = PromoteOp(Node->getOperand(0)); - Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, + Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1, DAG.getValueType(VT)); - Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); + Result = DAG.getNode(ISD::SRA, dl, NVT, Tmp1, Node->getOperand(1)); break; case ISD::SRL: // The input value must be properly zero extended. Tmp1 = PromoteOp(Node->getOperand(0)); - Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); - Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); + Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT); + Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, Node->getOperand(1)); break; case ISD::VAARG: @@ -4858,13 +4859,13 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); // Increment the pointer, VAList, to the next vaarg - Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, + Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, DAG.getConstant(VT.getSizeInBits()/8, TLI.getPointerTy())); // Store the incremented VAList to the legalized pointer - Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); + Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0); // Load the actual argument out of the pointer VAList - Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); + Result = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Tmp3, VAList, NULL, 0, VT); } // Remember that we legalized the chain. AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); @@ -4874,7 +4875,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { LoadSDNode *LD = cast<LoadSDNode>(Node); ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) ? ISD::EXTLOAD : LD->getExtensionType(); - Result = DAG.getExtLoad(ExtType, NVT, + Result = DAG.getExtLoad(ExtType, dl, NVT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(), LD->getSrcValueOffset(), LD->getMemoryVT(), @@ -4894,20 +4895,20 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { // Ensure that the resulting node is at least the same size as the operands' // value types, because we cannot assume that TLI.getSetCCValueType() is // constant. - Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3); + Result = DAG.getNode(ISD::SELECT, dl, VT2, Node->getOperand(0), Tmp2, Tmp3); break; } case ISD::SELECT_CC: Tmp2 = PromoteOp(Node->getOperand(2)); // True Tmp3 = PromoteOp(Node->getOperand(3)); // False - Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), + Result = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0), Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); break; case ISD::BSWAP: Tmp1 = Node->getOperand(0); - Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); - Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); - Result = DAG.getNode(ISD::SRL, NVT, Tmp1, + Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); + Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); + Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, DAG.getConstant(NVT.getSizeInBits() - VT.getSizeInBits(), TLI.getShiftAmountTy())); @@ -4916,24 +4917,24 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { case ISD::CTTZ: case ISD::CTLZ: // Zero extend the argument - Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); + Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); // Perform the larger operation, then subtract if needed. - Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); + Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); switch(Node->getOpcode()) { case ISD::CTPOP: Result = Tmp1; break; case ISD::CTTZ: // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) - Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, + Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), ISD::SETEQ); - Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, + Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); break; case ISD::CTLZ: //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) - Result = DAG.getNode(ISD::SUB, NVT, Tmp1, + Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, DAG.getConstant(NVT.getSizeInBits() - VT.getSizeInBits(), NVT)); break; @@ -5385,7 +5386,8 @@ void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, /// The resultant code need not be legal. SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, MVT SlotVT, - MVT DestVT) { + MVT DestVT, + DebugLoc dl) { // Create the stack frame object. unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment( SrcOp.getValueType().getTypeForMVT()); @@ -5406,24 +5408,25 @@ SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, SDValue Store; if (SrcSize > SlotSize) - Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, + Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, SV, 0, SlotVT, false, SrcAlign); else { assert(SrcSize == SlotSize && "Invalid store"); - Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, + Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, SV, 0, false, SrcAlign); } // Result is a load from the stack slot. if (SlotSize == DestSize) - return DAG.getLoad(DestVT, Store, FIPtr, SV, 0, false, DestAlign); + return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign); assert(SlotSize < DestSize && "Unknown extension!"); - return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, SV, 0, SlotVT, + return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT, false, DestAlign); } SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { + DebugLoc dl = Node->getDebugLoc(); // Create a vector sized/aligned stack slot, store the value to element #0, // then load the whole vector back out. SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); @@ -5431,9 +5434,10 @@ SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); int SPFI = StackPtrFI->getIndex(); - SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, + SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(0), + StackPtr, PseudoSourceValue::getFixedStack(SPFI), 0); - return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, + return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, PseudoSourceValue::getFixedStack(SPFI), 0); } @@ -5447,6 +5451,7 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { unsigned NumElems = Node->getNumOperands(); bool isOnlyLowElement = true; SDValue SplatValue = Node->getOperand(0); + DebugLoc dl = Node->getDebugLoc(); // FIXME: it would be far nicer to change this into map<SDValue,uint64_t> // and use a bitmask instead of a list of elements. @@ -5475,9 +5480,9 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { if (isOnlyLowElement) { // If the low element is an undef too, then this whole things is an undef. if (Node->getOperand(0).getOpcode() == ISD::UNDEF) - return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); + return DAG.getNode(ISD::UNDEF, dl, Node->getValueType(0)); // Otherwise, turn this into a scalar_to_vector node. - return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), + return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, Node->getValueType(0), Node->getOperand(0)); } @@ -5502,7 +5507,7 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { Constant *CP = ConstantVector::get(CV); SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); - return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, + return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, Alignment); } @@ -5512,17 +5517,19 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType()); std::vector<SDValue> ZeroVec(NumElems, Zero); - SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &ZeroVec[0], ZeroVec.size()); // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. if (isShuffleLegal(Node->getValueType(0), SplatMask)) { // Get the splatted value into the low element of a vector register. SDValue LowValVec = - DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); + DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, + Node->getValueType(0), SplatValue); // Return shuffle(LowValVec, undef, <0,0,0,0>) - return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, + Node->getValueType(0), LowValVec, DAG.getNode(ISD::UNDEF, Node->getValueType(0)), SplatMask); } @@ -5561,21 +5568,21 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { if (Val2.getOpcode() != ISD::UNDEF) MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); else - MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT); + MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, dl, MaskEltVT); - SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, + SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], MaskVec.size()); // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && isShuffleLegal(Node->getValueType(0), ShuffleMask)) { - Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); - Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); + Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val1); + Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val2); SDValue Ops[] = { Val1, Val2, ShuffleMask }; // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) - return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3); + return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,Node->getValueType(0), Ops, 3); } } @@ -5599,33 +5606,34 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { unsigned Offset = TypeByteSize*i; SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); - Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); + Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); - Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, - SV, Offset)); + Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i), + Idx, SV, Offset)); } SDValue StoreChain; if (!Stores.empty()) // Not all undef elements? - StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, + StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], Stores.size()); else StoreChain = DAG.getEntryNode(); // Result is a load from the stack slot. - return DAG.getLoad(VT, StoreChain, FIPtr, SV, 0); + return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0); } void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt, - SDValue &Lo, SDValue &Hi) { + SDValue &Lo, SDValue &Hi, + DebugLoc dl) { // Expand the subcomponents. SDValue LHSL, LHSH; ExpandOp(Op, LHSL, LHSH); SDValue Ops[] = { LHSL, LHSH, Amt }; MVT VT = LHSL.getValueType(); - Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); + Lo = DAG.getNode(NodeOp, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); Hi = Lo.getValue(1); } @@ -5635,7 +5643,8 @@ void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, /// libcall on this target, return false. Otherwise, return true with the /// low-parts expanded into Lo and Hi. bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, - SDValue &Lo, SDValue &Hi) { + SDValue &Lo, SDValue &Hi, + DebugLoc dl) { assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && "This is not a shift!"); @@ -5659,15 +5668,17 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, Hi = DAG.getConstant(0, NVT); } else if (Cst > NVTBits) { Lo = DAG.getConstant(0, NVT); - Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); + Hi = DAG.getNode(ISD::SHL, dl, + NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); } else if (Cst == NVTBits) { Lo = DAG.getConstant(0, NVT); Hi = InL; } else { - Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); - Hi = DAG.getNode(ISD::OR, NVT, - DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), - DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); + Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)); + Hi = DAG.getNode(ISD::OR, dl, NVT, + DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)), + DAG.getNode(ISD::SRL, dl, NVT, InL, + DAG.getConstant(NVTBits-Cst, ShTy))); } return true; case ISD::SRL: @@ -5675,36 +5686,39 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, Lo = DAG.getConstant(0, NVT); Hi = DAG.getConstant(0, NVT); } else if (Cst > NVTBits) { - Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); + Lo = DAG.getNode(ISD::SRL, dl, NVT, + InH, DAG.getConstant(Cst-NVTBits,ShTy)); Hi = DAG.getConstant(0, NVT); } else if (Cst == NVTBits) { Lo = InH; Hi = DAG.getConstant(0, NVT); } else { - Lo = DAG.getNode(ISD::OR, NVT, - DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), - DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); - Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); + Lo = DAG.getNode(ISD::OR, dl, NVT, + DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)), + DAG.getNode(ISD::SHL, dl, NVT, InH, + DAG.getConstant(NVTBits-Cst, ShTy))); + Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)); } return true; case ISD::SRA: if (Cst > VTBits) { - Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, + Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(NVTBits-1, ShTy)); } else if (Cst > NVTBits) { - Lo = DAG.getNode(ISD::SRA, NVT, InH, + Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst-NVTBits, ShTy)); - Hi = DAG.getNode(ISD::SRA, NVT, InH, + Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(NVTBits-1, ShTy)); } else if (Cst == NVTBits) { Lo = InH; - Hi = DAG.getNode(ISD::SRA, NVT, InH, + Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(NVTBits-1, ShTy)); } else { - Lo = DAG.getNode(ISD::OR, NVT, - DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), - DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); - Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); + Lo = DAG.getNode(ISD::OR, dl, NVT, + DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)), + DAG.getNode(ISD::SHL, dl, + NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); + Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst, ShTy)); } return true; } @@ -5720,7 +5734,7 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, // we can do this as a couple of simple shifts. if (KnownOne.intersects(Mask)) { // Mask out the high bit, which we know is set. - Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, + Amt = DAG.getNode(ISD::AND, dl, Amt.getValueType(), Amt, DAG.getConstant(~Mask, Amt.getValueType())); // Expand the incoming operand to be shifted, so that we have its parts @@ -5729,16 +5743,16 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, switch(Opc) { case ISD::SHL: Lo = DAG.getConstant(0, NVT); // Low part is zero. - Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. + Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. return true; case ISD::SRL: Hi = DAG.getConstant(0, NVT); // Hi part is zero. - Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. + Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. return true; case ISD::SRA: - Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. + Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. DAG.getConstant(NVTBits-1, Amt.getValueType())); - Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. + Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. return true; } } @@ -5747,7 +5761,7 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, // do this as a couple of simple shifts. if ((KnownZero & Mask) == Mask) { // Compute 32-amt. - SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), + SDValue Amt2 = DAG.getNode(ISD::SUB, dl, Amt.getValueType(), DAG.getConstant(NVTBits, Amt.getValueType()), Amt); @@ -5756,22 +5770,22 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, ExpandOp(Op, InL, InH); switch(Opc) { case ISD::SHL: - Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); - Hi = DAG.getNode(ISD::OR, NVT, - DAG.getNode(ISD::SHL, NVT, InH, Amt), - DAG.getNode(ISD::SRL, NVT, InL, Amt2)); + Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); + Hi = DAG.getNode(ISD::OR, dl, NVT, + DAG.getNode(ISD::SHL, dl, NVT, InH, Amt), + DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2)); return true; case ISD::SRL: - Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); - Lo = DAG.getNode(ISD::OR, NVT, - DAG.getNode(ISD::SRL, NVT, InL, Amt), - DAG.getNode(ISD::SHL, NVT, InH, Amt2)); + Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); + Lo = DAG.getNode(ISD::OR, dl, NVT, + DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), + DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2)); return true; case ISD::SRA: - Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); - Lo = DAG.getNode(ISD::OR, NVT, - DAG.getNode(ISD::SRL, NVT, InL, Amt), - DAG.getNode(ISD::SHL, NVT, InH, Amt2)); + Hi = DAG.getNode(ISD::SRA, dl, NVT |