diff options
| -rw-r--r-- | lib/Target/PowerPC/PPC.td | 6 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCSubtarget.h | 2 |
2 files changed, 6 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index 8b9e3a7ac1..272f6d6a16 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -29,6 +29,8 @@ def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true", "Enable GPUL instructions">; def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", "Enable the fsqrt instruction">; +def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", + "Enable the stfiwx instruction">; //===----------------------------------------------------------------------===// // Register File Description @@ -58,10 +60,10 @@ def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>; def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>; def : Processor<"750", G3Itineraries, []>; def : Processor<"970", G5Itineraries, - [FeatureAltivec, FeatureGPUL, FeatureFSqrt, + [FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX, Feature64Bit /*, Feature64BitRegs */]>; def : Processor<"g5", G5Itineraries, - [FeatureAltivec, FeatureGPUL, FeatureFSqrt, + [FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX, Feature64Bit /*, Feature64BitRegs */]>; diff --git a/lib/Target/PowerPC/PPCSubtarget.h b/lib/Target/PowerPC/PPCSubtarget.h index 3f1454ce52..4f838741ad 100644 --- a/lib/Target/PowerPC/PPCSubtarget.h +++ b/lib/Target/PowerPC/PPCSubtarget.h @@ -37,6 +37,7 @@ protected: bool Has64BitRegs; bool HasAltivec; bool HasFSQRT; + bool HasSTFIWX; bool IsAIX; bool IsDarwin; public: @@ -60,6 +61,7 @@ public: bool hasFSQRT() const { return HasFSQRT; } + bool hasSTFIWX() const { return HasSTFIWX; } bool has64BitRegs() const { return Has64BitRegs; } bool hasAltivec() const { return HasAltivec; } |