aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--lib/Target/Alpha/AlphaISelPattern.cpp133
-rw-r--r--lib/Target/Alpha/AlphaRegisterInfo.cpp10
-rw-r--r--lib/Target/IA64/IA64AsmPrinter.cpp32
-rw-r--r--lib/Target/IA64/IA64ISelPattern.cpp903
-rw-r--r--lib/Target/IA64/IA64InstrInfo.cpp2
-rw-r--r--lib/Target/IA64/IA64RegisterInfo.cpp12
-rw-r--r--lib/Target/IA64/IA64TargetMachine.cpp8
-rw-r--r--lib/Target/MRegisterInfo.cpp2
-rw-r--r--lib/Target/PowerPC/PPC32ISelSimple.cpp2
-rw-r--r--lib/Target/PowerPC/PPC64ISelPattern.cpp7
-rw-r--r--lib/Target/PowerPC/PPC64RegisterInfo.cpp2
-rw-r--r--lib/Target/PowerPC/PPCISelPattern.cpp7
-rw-r--r--lib/Target/PowerPC/PPCRegisterInfo.cpp2
-rw-r--r--lib/Target/Skeleton/SkeletonTargetMachine.cpp2
-rw-r--r--lib/Target/TargetInstrInfo.cpp12
-rw-r--r--lib/Target/TargetSchedInfo.cpp20
16 files changed, 578 insertions, 578 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 186daed496..450de9f491 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -132,7 +132,7 @@ namespace {
//collected in a memory argument list that is a naturally aligned
//array of quadwords. In a standard call, this list, if present, must
//be passed at 0(SP).
-//7 ... n 0(SP) ... (n-7)*8(SP)
+//7 ... n 0(SP) ... (n-7)*8(SP)
// //#define FP $15
// //#define RA $26
@@ -158,9 +158,9 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
//BuildMI(&BB, Alpha::IDEF, 0, Alpha::R26);
unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
- Alpha::R19, Alpha::R20, Alpha::R21};
+ Alpha::R19, Alpha::R20, Alpha::R21};
unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
- Alpha::F19, Alpha::F20, Alpha::F21};
+ Alpha::F19, Alpha::F20, Alpha::F21};
int count = 0;
//Def incoming registers
@@ -286,14 +286,15 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
std::pair<SDOperand, SDOperand>
AlphaTargetLowering::LowerCallTo(SDOperand Chain,
- const Type *RetTy, bool isVarArg,
- SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) {
+ const Type *RetTy, bool isVarArg,
+ SDOperand Callee, ArgListTy &Args,
+ SelectionDAG &DAG) {
int NumBytes = 0;
if (Args.size() > 6)
NumBytes = (Args.size() - 6) * 8;
Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
- DAG.getConstant(NumBytes, getPointerTy()));
+ DAG.getConstant(NumBytes, getPointerTy()));
std::vector<SDOperand> args_to_use;
for (unsigned i = 0, e = Args.size(); i != e; ++i)
{
@@ -911,11 +912,11 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
case ISD::FNEG:
if(ISD::FABS == N.getOperand(0).getOpcode())
{
- Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
- BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
+ Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+ BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
} else {
- Tmp1 = SelectExpr(N.getOperand(0));
- BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp1).addReg(Tmp1);
+ Tmp1 = SelectExpr(N.getOperand(0));
+ BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp1).addReg(Tmp1);
}
return Result;
@@ -1029,9 +1030,9 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
{
// Make sure we generate both values.
if (Result != notIn)
- ExprMap[N.getValue(1)] = notIn; // Generate the token
+ ExprMap[N.getValue(1)] = notIn; // Generate the token
else
- Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
+ Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
DestType = N.getValue(0).getValueType();
@@ -1449,12 +1450,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
case MVT::i16:
case MVT::i32:
case MVT::i64:
- BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
- break;
+ BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
+ break;
case MVT::f32:
case MVT::f64:
- BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F0).addReg(Alpha::F0);
- break;
+ BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F0).addReg(Alpha::F0);
+ break;
}
return Result+N.ResNo;
}
@@ -1571,7 +1572,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
bool isConst1 = false;
bool isConst2 = false;
int dir;
-
+
//Tmp1 = SelectExpr(N.getOperand(0));
if(N.getOperand(0).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 255)
@@ -1667,9 +1668,9 @@ unsigned ISel::SelectExpr(SDOperand N) {
// Make sure we generate both values.
if (Result != notIn)
- ExprMap[N.getValue(1)] = notIn; // Generate the token
+ ExprMap[N.getValue(1)] = notIn; // Generate the token
else
- Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
+ Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
SDOperand Chain = N.getOperand(0);
@@ -1685,11 +1686,11 @@ unsigned ISel::SelectExpr(SDOperand N) {
case ISD::XOR:
//Match Not
if (N.getOperand(1).getOpcode() == ISD::Constant &&
- cast<ConstantSDNode>(N.getOperand(1))->getSignExtended() == -1)
+ cast<ConstantSDNode>(N.getOperand(1))->getSignExtended() == -1)
{
- Tmp1 = SelectExpr(N.getOperand(0));
- BuildMI(BB, Alpha::ORNOT, 2, Result).addReg(Alpha::R31).addReg(Tmp1);
- return Result;
+ Tmp1 = SelectExpr(N.getOperand(0));
+ BuildMI(BB, Alpha::ORNOT, 2, Result).addReg(Alpha::R31).addReg(Tmp1);
+ return Result;
}
//Fall through
case ISD::AND:
@@ -1717,32 +1718,32 @@ unsigned ISel::SelectExpr(SDOperand N) {
//Check operand(0) == Not
if (N.getOperand(0).getOpcode() == ISD::XOR &&
N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
- cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getSignExtended() == -1)
+ cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getSignExtended() == -1)
{
- switch(opcode) {
- case ISD::AND: Opc = Alpha::BIC; break;
- case ISD::OR: Opc = Alpha::ORNOT; break;
- case ISD::XOR: Opc = Alpha::EQV; break;
- }
- Tmp1 = SelectExpr(N.getOperand(1));
- Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
- BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
- return Result;
+ switch(opcode) {
+ case ISD::AND: Opc = Alpha::BIC; break;
+ case ISD::OR: Opc = Alpha::ORNOT; break;
+ case ISD::XOR: Opc = Alpha::EQV; break;
+ }
+ Tmp1 = SelectExpr(N.getOperand(1));
+ Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
+ BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ return Result;
}
//Check operand(1) == Not
if (N.getOperand(1).getOpcode() == ISD::XOR &&
N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant &&
- cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getSignExtended() == -1)
+ cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getSignExtended() == -1)
{
- switch(opcode) {
- case ISD::AND: Opc = Alpha::BIC; break;
- case ISD::OR: Opc = Alpha::ORNOT; break;
- case ISD::XOR: Opc = Alpha::EQV; break;
- }
- Tmp1 = SelectExpr(N.getOperand(0));
- Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
- BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
- return Result;
+ switch(opcode) {
+ case ISD::AND: Opc = Alpha::BIC; break;
+ case ISD::OR: Opc = Alpha::ORNOT; break;
+ case ISD::XOR: Opc = Alpha::EQV; break;
+ }
+ Tmp1 = SelectExpr(N.getOperand(0));
+ Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
+ BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ return Result;
}
//Fall through
case ISD::SHL:
@@ -1930,11 +1931,11 @@ unsigned ISel::SelectExpr(SDOperand N) {
assert (SrcType == MVT::f32 || SrcType == MVT::f64);
Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
if (SrcType == MVT::f32)
- {
- Tmp2 = MakeReg(MVT::f64);
- BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1);
- Tmp1 = Tmp2;
- }
+ {
+ Tmp2 = MakeReg(MVT::f64);
+ BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1);
+ Tmp1 = Tmp2;
+ }
Tmp2 = MakeReg(MVT::f64);
BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Tmp1);
MoveFP2Int(Tmp2, Result, true);
@@ -1957,19 +1958,19 @@ unsigned ISel::SelectExpr(SDOperand N) {
if (CC.getOpcode() == ISD::SETCC &&
!MVT::isInteger(SetCC->getOperand(0).getValueType()))
{ //FP Setcc -> Int Select
- Tmp1 = MakeReg(MVT::f64);
+ Tmp1 = MakeReg(MVT::f64);
Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
- bool inv = SelectFPSetCC(CC, Tmp1);
- BuildMI(BB, inv?Alpha::CMOVNE_FP:Alpha::CMOVEQ_FP, 2, Result)
- .addReg(Tmp2).addReg(Tmp3).addReg(Tmp1);
- return Result;
+ bool inv = SelectFPSetCC(CC, Tmp1);
+ BuildMI(BB, inv?Alpha::CMOVNE_FP:Alpha::CMOVEQ_FP, 2, Result)
+ .addReg(Tmp2).addReg(Tmp3).addReg(Tmp1);
+ return Result;
}
if (CC.getOpcode() == ISD::SETCC) {
- //Int SetCC -> Select
- //Dropping the CC is only useful if we are comparing to 0
- if((SetCC->getOperand(1).getOpcode() == ISD::Constant &&
- cast<ConstantSDNode>(SetCC->getOperand(1))->getValue() == 0) ||
+ //Int SetCC -> Select
+ //Dropping the CC is only useful if we are comparing to 0
+ if((SetCC->getOperand(1).getOpcode() == ISD::Constant &&
+ cast<ConstantSDNode>(SetCC->getOperand(1))->getValue() == 0) ||
(SetCC->getOperand(0).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(SetCC->getOperand(0))->getValue() == 0))
{
@@ -2013,12 +2014,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
if (LeftConst) {
Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
BuildMI(BB, Opc, 2, Result).addReg(Tmp3)
- .addImm(cast<ConstantSDNode>(N.getOperand(1))->getValue())
+ .addImm(cast<ConstantSDNode>(N.getOperand(1))->getValue())
.addReg(Tmp1);
} else if (RightConst) {
Tmp3 = SelectExpr(N.getOperand(1)); //Use if FALSE
BuildMI(BB, Opc, 2, Result).addReg(Tmp3)
- .addImm(cast<ConstantSDNode>(N.getOperand(2))->getValue())
+ .addImm(cast<ConstantSDNode>(N.getOperand(2))->getValue())
.addReg(Tmp1);
} else {
Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
@@ -2027,7 +2028,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
}
return Result;
}
- //Otherwise, fall though
+ //Otherwise, fall though
}
Tmp1 = SelectExpr(N.getOperand(0)); //Cond
Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
@@ -2041,13 +2042,13 @@ unsigned ISel::SelectExpr(SDOperand N) {
{
int64_t val = (int64_t)cast<ConstantSDNode>(N)->getValue();
if (val <= IMM_HIGH && val >= IMM_LOW) {
- BuildMI(BB, Alpha::LDA, 2, Result).addImm(val).addReg(Alpha::R31);
+ BuildMI(BB, Alpha::LDA, 2, Result).addImm(val).addReg(Alpha::R31);
}
- else if (val <= (int64_t)IMM_HIGH + (int64_t)IMM_HIGH * (int64_t)IMM_MULT &&
- val >= (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT) {
- Tmp1 = MakeReg(MVT::i64);
- BuildMI(BB, Alpha::LDAH, 2, Tmp1).addImm(getUpper16(val)).addReg(Alpha::R31);
- BuildMI(BB, Alpha::LDA, 2, Result).addImm(getLower16(val)).addReg(Tmp1);
+ else if (val <= (int64_t)IMM_HIGH +(int64_t)IMM_HIGH* (int64_t)IMM_MULT &&
+ val >= (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT) {
+ Tmp1 = MakeReg(MVT::i64);
+ BuildMI(BB, Alpha::LDAH, 2, Tmp1).addImm(getUpper16(val)).addReg(Alpha::R31);
+ BuildMI(BB, Alpha::LDA, 2, Result).addImm(getLower16(val)).addReg(Tmp1);
}
else {
MachineConstantPool *CP = BB->getParent()->getConstantPool();
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index c9c32dd49d..7938a592fa 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -135,11 +135,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineInstr *New;
if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
- New=BuildMI(Alpha::LDA, 2, Alpha::R30)
+ New=BuildMI(Alpha::LDA, 2, Alpha::R30)
.addImm(-Amount).addReg(Alpha::R30);
} else {
- assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
- New=BuildMI(Alpha::LDA, 2, Alpha::R30)
+ assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
+ New=BuildMI(Alpha::LDA, 2, Alpha::R30)
.addImm(Amount).addReg(Alpha::R30);
}
@@ -272,8 +272,8 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
const MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
MachineInstr *MI;
- assert((MBBI->getOpcode() == Alpha::RET || MBBI->getOpcode() == Alpha::RETURN) &&
- "Can only insert epilog into returning blocks");
+ assert((MBBI->getOpcode() == Alpha::RET || MBBI->getOpcode() == Alpha::RETURN)
+ && "Can only insert epilog into returning blocks");
bool FP = hasFP(MF);
diff --git a/lib/Target/IA64/IA64AsmPrinter.cpp b/lib/Target/IA64/IA64AsmPrinter.cpp
index 5eaa6fab31..395fc89b8c 100644
--- a/lib/Target/IA64/IA64AsmPrinter.cpp
+++ b/lib/Target/IA64/IA64AsmPrinter.cpp
@@ -113,14 +113,14 @@ bool IA64SharedAsmPrinter::doFinalization(Module &M) {
I->hasWeakLinkage() /* FIXME: Verify correct */)) {
SwitchSection(O, CurSection, ".data");
if (I->hasInternalLinkage()) {
- O << "\t.lcomm " << name << "," << TD.getTypeSize(C->getType())
- << "," << (1 << Align);
- O << "\t\t// ";
- } else {
- O << "\t.common " << name << "," << TD.getTypeSize(C->getType())
- << "," << (1 << Align);
- O << "\t\t// ";
- }
+ O << "\t.lcomm " << name << "," << TD.getTypeSize(C->getType())
+ << "," << (1 << Align);
+ O << "\t\t// ";
+ } else {
+ O << "\t.common " << name << "," << TD.getTypeSize(C->getType())
+ << "," << (1 << Align);
+ O << "\t\t// ";
+ }
WriteAsOperand(O, I, true, true, &M);
O << "\n";
} else {
@@ -131,7 +131,7 @@ bool IA64SharedAsmPrinter::doFinalization(Module &M) {
O << "\t.weak " << name << "\n";
SwitchSection(O, CurSection, "");
O << "\t.section\t.llvm.linkonce.d." << name
- << ", \"aw\", \"progbits\"\n";
+ << ", \"aw\", \"progbits\"\n";
break;
case GlobalValue::AppendingLinkage:
// FIXME: appending linkage variables should go into a section of
@@ -352,19 +352,19 @@ void IA64AsmPrinter::printOp(const MachineOperand &MO,
bool Needfptr=false; // if we're computing an address @ltoff(X), do
// we need to decorate it so it becomes
- // @ltoff(@fptr(X)) ?
- if(F && !isBRCALLinsn /*&& F->isExternal()*/)
+ // @ltoff(@fptr(X)) ?
+ if (F && !isBRCALLinsn /*&& F->isExternal()*/)
Needfptr=true;
// if this is the target of a call instruction, we should define
// the function somewhere (GNU gas has no problem without this, but
// Intel ias rightly complains of an 'undefined symbol')
- if(F /*&& isBRCALLinsn*/ && F->isExternal())
+ if (F /*&& isBRCALLinsn*/ && F->isExternal())
ExternalFunctionNames.insert(Mang->getValueName(MO.getGlobal()));
else
- if(GV->isExternal()) // e.g. stuff like 'stdin'
- ExternalObjectNames.insert(Mang->getValueName(MO.getGlobal()));
+ if (GV->isExternal()) // e.g. stuff like 'stdin'
+ ExternalObjectNames.insert(Mang->getValueName(MO.getGlobal()));
if (!isBRCALLinsn)
O << "@ltoff(";
@@ -406,9 +406,9 @@ bool IA64AsmPrinter::doInitialization(Module &M) {
AsmPrinter::doInitialization(M);
O << "\n.ident \"LLVM-ia64\"\n\n"
- << "\t.psr lsb\n" // should be "msb" on HP-UX, for starters
+ << "\t.psr lsb\n" // should be "msb" on HP-UX, for starters
<< "\t.radix C\n"
- << "\t.psr abi64\n"; // we only support 64 bits for now
+ << "\t.psr abi64\n"; // we only support 64 bits for now
return false;
}
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index 0514c58626..7c03a45bca 100644
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -173,56 +173,56 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
{
SDOperand newroot, argt;
if(count < 8) { // need to fix this logic? maybe.
-
- switch (getValueType(I->getType())) {
- default:
- std::cerr << "ERROR in LowerArgs: unknown type "
- << getValueType(I->getType()) << "\n";
- abort();
- case MVT::f32:
- // fixme? (well, will need to for weird FP structy stuff,
- // see intel ABI docs)
- case MVT::f64:
-//XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
- MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn
- // floating point args go into f8..f15 as-needed, the increment
- argVreg[count] = // is below..:
- MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
- // FP args go into f8..f15 as needed: (hence the ++)
- argPreg[count] = args_FP[used_FPArgs++];
- argOpc[count] = IA64::FMOV;
- argt = newroot = DAG.getCopyFromReg(argVreg[count],
- getValueType(I->getType()), DAG.getRoot());
- break;
- case MVT::i1: // NOTE: as far as C abi stuff goes,
- // bools are just boring old ints
- case MVT::i8:
- case MVT::i16:
- case MVT::i32:
- case MVT::i64:
-//XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
- MF.addLiveIn(args_int[count]); // mark this register as liveIn
- argVreg[count] =
- MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
- argPreg[count] = args_int[count];
- argOpc[count] = IA64::MOV;
- argt = newroot =
- DAG.getCopyFromReg(argVreg[count], MVT::i64, DAG.getRoot());
- if ( getValueType(I->getType()) != MVT::i64)
- argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
- newroot);
- break;
- }
+
+ switch (getValueType(I->getType())) {
+ default:
+ std::cerr << "ERROR in LowerArgs: unknown type "
+ << getValueType(I->getType()) << "\n";
+ abort();
+ case MVT::f32:
+ // fixme? (well, will need to for weird FP structy stuff,
+ // see intel ABI docs)
+ case MVT::f64:
+//XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
+ MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn
+ // floating point args go into f8..f15 as-needed, the increment
+ argVreg[count] = // is below..:
+ MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
+ // FP args go into f8..f15 as needed: (hence the ++)
+ argPreg[count] = args_FP[used_FPArgs++];
+ argOpc[count] = IA64::FMOV;
+ argt = newroot = DAG.getCopyFromReg(argVreg[count],
+ getValueType(I->getType()), DAG.getRoot());
+ break;
+ case MVT::i1: // NOTE: as far as C abi stuff goes,
+ // bools are just boring old ints
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
+ case MVT::i64:
+//XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
+ MF.addLiveIn(args_int[count]); // mark this register as liveIn
+ argVreg[count] =
+ MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
+ argPreg[count] = args_int[count];
+ argOpc[count] = IA64::MOV;
+ argt = newroot =
+ DAG.getCopyFromReg(argVreg[count], MVT::i64, DAG.getRoot());
+ if ( getValueType(I->getType()) != MVT::i64)
+ argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
+ newroot);
+ break;
+ }
} else { // more than 8 args go into the frame
- // Create the frame index object for this incoming parameter...
- ArgOffset = 16 + 8 * (count - 8);
- int FI = MFI->CreateFixedObject(8, ArgOffset);
-
- // Create the SelectionDAG nodes corresponding to a load
- //from this parameter
- SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
- argt = newroot = DAG.getLoad(getValueType(I->getType()),
- DAG.getEntryNode(), FIN);
+ // Create the frame index object for this incoming parameter...
+ ArgOffset = 16 + 8 * (count - 8);
+ int FI = MFI->CreateFixedObject(8, ArgOffset);
+
+ // Create the SelectionDAG nodes corresponding to a load
+ //from this parameter
+ SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
+ argt = newroot = DAG.getLoad(getValueType(I->getType()),
+ DAG.getEntryNode(), FIN);
}
++count;
DAG.setRoot(newroot.getValue(1));
@@ -296,8 +296,9 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
std::pair<SDOperand, SDOperand>
IA64TargetLowering::LowerCallTo(SDOperand Chain,
- const Type *RetTy, bool isVarArg,
- SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) {
+ const Type *RetTy, bool isVarArg,
+ SDOperand Callee, ArgListTy &Args,
+ SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
@@ -330,18 +331,18 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain,
case MVT::i8:
case MVT::i16:
case MVT::i32:
- //promote to 64-bits, sign/zero extending based on type
- //of the argument
- if(Args[i].second->isSigned())
- Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64,
- Args[i].first);
- else
- Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64,
- Args[i].first);
- break;
+ //promote to 64-bits, sign/zero extending based on type
+ //of the argument
+ if(Args[i].second->isSigned())
+ Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64,
+ Args[i].first);
+ else
+ Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64,
+ Args[i].first);
+ break;
case MVT::f32:
- //promote to 64-bits
- Args[i].first = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Args[i].first);
+ //promote to 64-bits
+ Args[i].first = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Args[i].first);
case MVT::f64:
case MVT::i64:
break;
@@ -356,7 +357,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain,
RetVals.push_back(MVT::Other);
SDOperand TheCall = SDOperand(DAG.getCall(RetVals, Chain,
- Callee, args_to_use), 0);
+ Callee, args_to_use), 0);
Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
DAG.getConstant(NumBytes, getPointerTy()));
@@ -593,7 +594,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
if (Tmp1 != Result)
// we multiply by +1.0, negate (this is FNMA), and then add 0.0
BuildMI(BB, IA64::FNMA, 3, Result).addReg(Tmp1).addReg(IA64::F1)
- .addReg(IA64::F0);
+ .addReg(IA64::F0);
return Result;
}
@@ -622,7 +623,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
if (CN->getValue() < 32000)
{
BuildMI(BB, IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
- .addImm(-CN->getValue());
+ .addImm(-CN->getValue());
} else {
Tmp1 = SelectExpr(N.getOperand(1));
// Subtract size from stack pointer, thereby allocating some space.
@@ -652,19 +653,19 @@ unsigned ISel::SelectExpr(SDOperand N) {
unsigned bogoResult;
switch (N.getOperand(1).getValueType()) {
- default: assert(0 &&
- "ISD::SELECT: 'select'ing something other than i64 or f64!\n");
- case MVT::i64:
- bogoResult=MakeReg(MVT::i64);
- break;
- case MVT::f64:
- bogoResult=MakeReg(MVT::f64);
- break;
+ default: assert(0 &&
+ "ISD::SELECT: 'select'ing something other than i64 or f64!\n");
+ case MVT::i64:
+ bogoResult=MakeReg(MVT::i64);
+ break;
+ case MVT::f64:
+ bogoResult=MakeReg(MVT::f64);
+ break;
}
BuildMI(BB, IA64::MOV, 1, bogoResult).addReg(Tmp3);
BuildMI(BB, IA64::CMOV, 2, Result).addReg(bogoResult).addReg(Tmp2)
- .addReg(Tmp1); // FIXME: should be FMOV/FCMOV sometimes,
+ .addReg(Tmp1); // FIXME: should be FMOV/FCMOV sometimes,
// though this will work for now (no JIT)
return Result;
}
@@ -675,15 +676,13 @@ unsigned ISel::SelectExpr(SDOperand N) {
switch (N.getValueType()) {
default: assert(0 && "Cannot use constants of this type!");
case MVT::i1: { // if a bool, we don't 'load' so much as generate
- // the constant:
- if(cast<ConstantSDNode>(N)->getValue()) // true:
- BuildMI(BB, IA64::CMPEQ, 2, Result)
- .addReg(IA64::r0).addReg(IA64::r0);
- else // false:
- BuildMI(BB, IA64::CMPNE, 2, Result)
- .addReg(IA64::r0).addReg(IA64::r0);
- return Result; // early exit
- }
+ // the constant:
+ if(cast<ConstantSDNode>(N)->getValue()) // true:
+ BuildMI(BB, IA64::CMPEQ, 2, Result).addReg(IA64::r0).addReg(IA64::r0);
+ else // false:
+ BuildMI(BB, IA64::CMPNE, 2, Result).addReg(IA64::r0).addReg(IA64::r0);
+ return Result; // early exit
+ }
case MVT::i64: break;
}
@@ -753,14 +752,14 @@ unsigned ISel::SelectExpr(SDOperand N) {
// we handle bools differently! :
case MVT::i1: { // if the predicate reg has 1, we want a '1' in our GR.
- unsigned dummy = MakeReg(MVT::i64);
- // first load zero:
- BuildMI(BB, IA64::MOV, 1, dummy).addReg(IA64::r0);
- // ...then conditionally (PR:Tmp1) add 1:
- BuildMI(BB, IA64::TPCADDIMM22, 2, Result).addReg(dummy)
- .addImm(1).addReg(Tmp1);
- return Result; // XXX early exit!
- }
+ unsigned dummy = MakeReg(MVT::i64);
+ // first load zero:
+ BuildMI(BB, IA64::MOV, 1, dummy).addReg(IA64::r0);
+ // ...then conditionally (PR:Tmp1) add 1:
+ BuildMI(BB, IA64::TPCADDIMM22, 2, Result).addReg(dummy)
+ .addImm(1).addReg(Tmp1);
+ return Result; // XXX early exit!
+ }
}
BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
@@ -776,8 +775,8 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
switch (N.getOperand(0).getValueType()) {
default: assert(0 && "Cannot sign-extend this type!");
case MVT::i1: assert(0 && "trying to sign extend a bool? ow.\n");
- Opc = IA64::SXT1; break;
- // FIXME: for now, we treat bools the same as i8s
+ Opc = IA64::SXT1; break;
+ // FIXME: for now, we treat bools the same as i8s
case MVT::i8: Opc = IA64::SXT1; break;
case MVT::i16: Opc = IA64::SXT2; break;
case MVT::i32: Opc = IA64::SXT4; break;
@@ -801,10 +800,10 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
default: assert(0 && "Unknown truncate!");
case MVT::i1: {
// if input (normal reg) is 0, 0!=0 -> false (0), if 1, 1!=0 ->true (1):
- BuildMI(BB, IA64::CMPNE, 2, Result).addReg(Tmp1)
- .addReg(IA64::r0);
- return Result; // XXX early exit!
- }
+ BuildMI(BB, IA64::CMPNE, 2, Result).addReg(Tmp1)
+ .addReg(IA64::r0);
+ return Result; // XXX early exit!
+ }
case MVT::i8: depositPos=0; depositLen=8; break;
case MVT::i16: depositPos=0; depositLen=16; break;
case MVT::i32: depositPos=0; depositLen=32; break;
@@ -814,10 +813,10 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
return Result;
}
-/*
+/*
case ISD::FP_ROUND: {
assert (DestType == MVT::f32 && N.getOperand(0).getValueType() == MVT::f64 &&
- "error: trying to FP_ROUND something other than f64 -> f32!\n");
+ "error: trying to FP_ROUND something other than f64 -> f32!\n");
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, IA64::FADDS, 2, Result).addReg(Tmp1).addReg(IA64::F0);
// we add 0.0 using a single precision add to do rounding
@@ -875,20 +874,20 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
}
if(DestType != MVT::f64 && N.getOperand(0).getOpcode() == ISD::SHL &&
- N.getOperand(0).Val->hasOneUse()) { // if we might be able to fold
+ N.getOperand(0).Val->hasOneUse()) { // if we might be able to fold
// this add into a shladd, try:
ConstantSDNode *CSD = NULL;
if((CSD = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) &&
- (CSD->getValue() >= 1) && (CSD->getValue() <= 4) ) { // we can:
-
- // ++FusedSHLADD; // Statistic
- Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
- int shl_amt = CSD->getValue();
- Tmp3 = SelectExpr(N.getOperand(1));
-
- BuildMI(BB, IA64::SHLADD, 3, Result)
- .addReg(Tmp1).addImm(shl_amt).addReg(Tmp3);
- return Result; // early exit
+ (CSD->getValue() >= 1) && (CSD->getValue() <= 4) ) { // we can:
+
+ // ++FusedSHLADD; // Statistic
+ Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+ int shl_amt = CSD->getValue();
+ Tmp3 = SelectExpr(N.getOperand(1));
+
+ BuildMI(BB, IA64::SHLADD, 3, Result)
+ .addReg(Tmp1).addImm(shl_amt).addReg(Tmp3);
+ return Result; // early exit
}
}
@@ -896,12 +895,12 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
Tmp1 = SelectExpr(N.getOperand(0));
if(DestType != MVT::f64) { // integer addition:
switch (ponderIntegerAdditionWith(N.getOperand(1), Tmp3)) {
- case 1: // adding a constant that's 14 bits
- BuildMI(BB, IA64::ADDIMM14, 2, Result).addReg(Tmp1).addSImm(Tmp3);
- return Result; // early exit
- } // fallthrough and emit a reg+reg ADD:
- Tmp2 = SelectExpr(N.getOperand(1));
- BuildMI(BB, IA64::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ case 1: // adding a constant that's 14 bits
+ BuildMI(BB, IA64::ADDIMM14, 2, Result).addReg(Tmp1).addSImm(Tmp3);
+ return Result; // early exit
+ } // fallthrough and emit a reg+reg ADD:
+ Tmp2 = SelectExpr(N.getOperand(1));
+ BuildMI(BB, IA64::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
} else { // this is a floating point addition
Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, IA64::FADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
@@ -921,7 +920,7 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
BuildMI(BB, IA64::SETFSIG, 1, TempFR1).addReg(Tmp1);
BuildMI(BB, IA64::SETFSIG, 1, TempFR2).addReg(Tmp2);
BuildMI(BB, IA64::XMAL, 1, TempFR3).addReg(TempFR1).addReg(TempFR2)
- .addReg(IA64::F0);
+ .addReg(IA64::F0);
BuildMI(BB, IA64::GETFSIG, 1, Result).addReg(TempFR3);
}
else // floating point multiply
@@ -943,12 +942,12 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
Tmp2 = SelectExpr(N.getOperand(1));
if(DestType != MVT::f64) { // integer subtraction:
switch (ponderIntegerSubtractionFrom(N.getOperand(0), Tmp3)) {
- case 1: // subtracting *from* an 8 bit constant:
- BuildMI(BB, IA64::SUBIMM8, 2, Result).addSImm(Tmp3).addReg(Tmp2);
- return Result; // early exit
- } // fallthrough and emit a reg+reg SUB:
- Tmp1 = SelectExpr(N.getOperand(0));
- BuildMI(BB, IA64::SUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ case 1: // subtracting *from* an 8 bit constant:
+ BuildMI(BB, IA64::SUBIMM8, 2, Result).addSImm(Tmp3).addReg(Tmp2);
+ return Result; // early exit
+ } // fallthrough and emit a reg+reg SUB:
+ Tmp1 = SelectExpr(N.getOperand(0));
+ BuildMI(BB, IA64::SUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
} else { // this is a floating point subtraction
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, IA64::FSUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
@@ -976,7 +975,7 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
return Result;
}
-
+
case ISD::AND: {
switch (N.getValueType()) {
default: assert(0 && "Cannot AND this type!");
@@ -1002,13 +1001,13 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
unsigned bogusTemp4 = MakeReg(MVT::i1);
BuildMI(BB, IA64::PCMPEQUNC, 3, bogusTemp1)
- .addReg(IA64::r0).addReg(IA64::r0).addReg(pA);
+ .addReg(IA64::r0).addReg(IA64::r0).addReg(pA);
BuildMI(BB, IA64::CMPEQ, 2, bogusTemp2)
- .addReg(IA64::r0).addReg(IA64::r0);
+ .addReg(IA64::r0).addReg(IA64::r0);
BuildMI(BB, IA64::TPCMPNE, 3, pTemp)
- .addReg(bogusTemp2).addReg(IA64::r0).addReg(IA64::r0).addReg(pB);
+ .addReg(bogusTemp2).addReg(IA64::r0).addReg(IA64::r0).addReg(pB);
BuildMI(BB, IA64::TPCMPNE, 3, Result)
- .addReg(bogusTemp1).addReg(IA64::r0).addReg(IA64::r0).addReg(pTemp);
+ .addReg(bogusTemp1).addReg(IA64::r0).addReg(IA64::r0).addReg(pTemp);
break;
}
@@ -1020,22 +1019,22 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
Tmp1 = SelectExpr(N.getOperand(0));
switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) {
case 1: // ANDing a constant that is 2^n-1 for some n
- switch (Tmp3) {
- case 8: // if AND 0x00000000000000FF, be quaint and use