diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 20b9a588e2..88596d65db 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1728,7 +1728,7 @@ SDOperand DAGCombiner::visitSHL(SDNode *N) { // if (shl x, c) is known to be zero, return 0 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) return DAG.getConstant(0, VT); - if (SimplifyDemandedBits(SDOperand(N, 0))) + if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) return SDOperand(N, 0); // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) if (N1C && N0.getOpcode() == ISD::SHL && @@ -1907,6 +1907,12 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) { return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); } } + + // fold operands of srl based on knowledge that the low bits are not + // demanded. + if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) + return SDOperand(N, 0); + return SDOperand(); } |