diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index de7306c9d3..a7dbe99231 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -17,7 +17,8 @@ include "PowerPCInstrFormats.td" //===----------------------------------------------------------------------===// // Selection DAG Type Constraint definitions. // -// Note that the semantics of these constraints are hard coded into tblgen. +// Note that the semantics of these constraints are hard coded into tblgen. To +// modify or add constraints, you have to hack tblgen. // class SDTypeConstraint<int opnum> { @@ -66,7 +67,9 @@ class SDTypeProfile<int numresults, int numoperands, // Builtin profiles. def SDTImm : SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. def SDTVT : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt' -def SDTBinOp : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>]>; +def SDTBinOp : SDTypeProfile<1, 2, [ // add, mul, etc. + SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> +]>; def SDTIntBinOp : SDTypeProfile<1, 2, [ // and, or, xor, udiv, etc. SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> ]>; |