diff options
| -rw-r--r-- | include/llvm/CodeGen/SelectionDAGNodes.h | 3 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 12 |
2 files changed, 13 insertions, 2 deletions
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index 94ef5d5901..3af9008a43 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -308,6 +308,9 @@ namespace ISD { PCMARKER, // READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. + // The only operand is a chain and a value and a chain are produced. The + // value is the contents of the architecture specific cycle counter like + // register (or other high accuracy low latency clock source) READCYCLECOUNTER, // READPORT, WRITEPORT, READIO, WRITEIO - These correspond to the LLVM diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index ae61e20896..01e76c1b42 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -804,9 +804,17 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); return 0; } - case Intrinsic::readcyclecounter: - setValue(&I, DAG.getNode(ISD::READCYCLECOUNTER, MVT::i64, getRoot())); + case Intrinsic::readcyclecounter: { + std::vector<MVT::ValueType> VTs; + VTs.push_back(MVT::i64); + VTs.push_back(MVT::Other); + std::vector<SDOperand> Ops; + Ops.push_back(getRoot()); + SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, Ops); + setValue(&I, Tmp); + DAG.setRoot(Tmp.getValue(1)); return 0; + } case Intrinsic::cttz: setValue(&I, DAG.getNode(ISD::CTTZ, getValue(I.getOperand(1)).getValueType(), |