diff options
| -rw-r--r-- | lib/Target/ARM/ARMMachineFunctionInfo.h | 16 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 6 |
2 files changed, 17 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMMachineFunctionInfo.h b/lib/Target/ARM/ARMMachineFunctionInfo.h index 05dc0dccde..6ce4d532ff 100644 --- a/lib/Target/ARM/ARMMachineFunctionInfo.h +++ b/lib/Target/ARM/ARMMachineFunctionInfo.h @@ -36,6 +36,10 @@ class ARMFunctionInfo : public MachineFunctionInfo { /// processFunctionBeforeCalleeSavedScan(). bool HasStackFrame; + /// LRSpilled - True if the LR register has been spilled. + /// + bool LRSpilled; + /// FramePtrSpillOffset - If HasStackFrame, this records the frame pointer /// spill stack offset. unsigned FramePtrSpillOffset; @@ -71,14 +75,14 @@ class ARMFunctionInfo : public MachineFunctionInfo { public: ARMFunctionInfo() : isThumb(false), - VarArgsRegSaveSize(0), HasStackFrame(false), FramePtrSpillOffset(0), - GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0), + VarArgsRegSaveSize(0), HasStackFrame(false), LRSpilled(false), + FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0), GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0), JumpTableUId(0) {} ARMFunctionInfo(MachineFunction &MF) : isThumb(MF.getTarget().getSubtarget<ARMSubtarget>().isThumb()), - VarArgsRegSaveSize(0), HasStackFrame(false), FramePtrSpillOffset(0), - GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0), + VarArgsRegSaveSize(0), HasStackFrame(false), LRSpilled(false), + FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0), GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0), JumpTableUId(0) {} bool isThumbFunction() const { return isThumb; } @@ -88,6 +92,10 @@ public: bool hasStackFrame() const { return HasStackFrame; } void setHasStackFrame(bool s) { HasStackFrame = s; } + + bool isLRSpilled() const { return LRSpilled; } + void setLRIsSpilled(bool s) { LRSpilled = s; } + unsigned getFramePtrSpillOffset() const { return FramePtrSpillOffset; } void setFramePtrSpillOffset(unsigned o) { FramePtrSpillOffset = o; } diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 912d17adc1..2accaf890e 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -769,13 +769,14 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const { } } + ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); if (!CanEliminateFrame) { - ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); AFI->setHasStackFrame(true); // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. // Spill LR as well so we can fold BX_RET to the registers restore (LDM). if (!LRSpilled && CS1Spilled) { + LRSpilled = true; MF.changePhyRegUsed(ARM::LR, true); NumGPRSpills++; UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), @@ -798,6 +799,9 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const { MF.changePhyRegUsed(UnspilledCS2GPRs.front(), true); } } + + // Remembe if LR has been spilled. + AFI->setLRIsSpilled(LRSpilled); } /// Move iterator pass the next bunch of callee save load / store ops for |