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authorChris Lattner <sabre@nondot.org>2010-03-19 01:00:55 +0000
committerChris Lattner <sabre@nondot.org>2010-03-19 01:00:55 +0000
commit6a91b18e5777f39e52e93221453abfa4553b6f93 (patch)
tree070047b9095180904bfa4bf499a94a8c7cd7025d /utils
parent01dcecc214918b29cf3712420457fef309eeaad6 (diff)
make inst_begin/inst_end iterate over InstructionsByEnumValue.
Use CodeGenTarget::getInstNamespace in one place and fix it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98915 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils')
-rw-r--r--utils/TableGen/AsmWriterEmitter.cpp6
-rw-r--r--utils/TableGen/CodeGenTarget.cpp47
-rw-r--r--utils/TableGen/CodeGenTarget.h18
-rw-r--r--utils/TableGen/InstrEnumEmitter.cpp9
-rw-r--r--utils/TableGen/InstrInfoEmitter.cpp4
5 files changed, 39 insertions, 45 deletions
diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp
index 9378343cec..ab1e239a95 100644
--- a/utils/TableGen/AsmWriterEmitter.cpp
+++ b/utils/TableGen/AsmWriterEmitter.cpp
@@ -254,10 +254,10 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
E = Target.inst_end(); I != E; ++I)
- if (!I->second.AsmString.empty() &&
- I->second.TheDef->getName() != "PHI")
+ if (!(*I)->AsmString.empty() &&
+ (*I)->TheDef->getName() != "PHI")
Instructions.push_back(
- AsmWriterInst(I->second,
+ AsmWriterInst(**I,
AsmWriter->getValueAsInt("Variant"),
AsmWriter->getValueAsInt("FirstOperandColumn"),
AsmWriter->getValueAsInt("OperandSpacing")));
diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp
index 36a9d1ef92..d697217ff6 100644
--- a/utils/TableGen/CodeGenTarget.cpp
+++ b/utils/TableGen/CodeGenTarget.cpp
@@ -120,18 +120,14 @@ const std::string &CodeGenTarget::getName() const {
}
std::string CodeGenTarget::getInstNamespace() const {
- std::string InstNS;
-
for (inst_iterator i = inst_begin(), e = inst_end(); i != e; ++i) {
- InstNS = i->second.Namespace;
-
- // Make sure not to pick up "TargetInstrInfo" by accidentally getting
+ // Make sure not to pick up "TargetOpcode" by accidentally getting
// the namespace off the PHI instruction or something.
- if (InstNS != "TargetInstrInfo")
- break;
+ if ((*i)->Namespace != "TargetOpcode")
+ return (*i)->Namespace;
}
- return InstNS;
+ return "";
}
Record *CodeGenTarget::getInstructionSet() const {
@@ -300,7 +296,7 @@ GetInstByName(const char *Name,
/// getInstructionsByEnumValue - Return all of the instructions defined by the
/// target, ordered by their enum value.
-void CodeGenTarget::ComputeInstrsByEnum() {
+void CodeGenTarget::ComputeInstrsByEnum() const {
const std::map<std::string, CodeGenInstruction> &Insts = getInstructions();
const CodeGenInstruction *PHI = GetInstByName("PHI", Insts);
const CodeGenInstruction *INLINEASM = GetInstByName("INLINEASM", Insts);
@@ -332,20 +328,25 @@ void CodeGenTarget::ComputeInstrsByEnum() {
InstrsByEnum.push_back(SUBREG_TO_REG);
InstrsByEnum.push_back(COPY_TO_REGCLASS);
InstrsByEnum.push_back(DBG_VALUE);
- for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
- if (&II->second != PHI &&
- &II->second != INLINEASM &&
- &II->second != DBG_LABEL &&
- &II->second != EH_LABEL &&
- &II->second != GC_LABEL &&
- &II->second != KILL &&
- &II->second != EXTRACT_SUBREG &&
- &II->second != INSERT_SUBREG &&
- &II->second != IMPLICIT_DEF &&
- &II->second != SUBREG_TO_REG &&
- &II->second != COPY_TO_REGCLASS &&
- &II->second != DBG_VALUE)
- InstrsByEnum.push_back(&II->second);
+
+ for (std::map<std::string, CodeGenInstruction>::const_iterator
+ I = Insts.begin(), E = Insts.end(); I != E; ++I) {
+ const CodeGenInstruction *CGI = &I->second;
+
+ if (CGI != PHI &&
+ CGI != INLINEASM &&
+ CGI != DBG_LABEL &&
+ CGI != EH_LABEL &&
+ CGI != GC_LABEL &&
+ CGI != KILL &&
+ CGI != EXTRACT_SUBREG &&
+ CGI != INSERT_SUBREG &&
+ CGI != IMPLICIT_DEF &&
+ CGI != SUBREG_TO_REG &&
+ CGI != COPY_TO_REGCLASS &&
+ CGI != DBG_VALUE)
+ InstrsByEnum.push_back(CGI);
+ }
}
diff --git a/utils/TableGen/CodeGenTarget.h b/utils/TableGen/CodeGenTarget.h
index ac6574d69a..a0e631e109 100644
--- a/utils/TableGen/CodeGenTarget.h
+++ b/utils/TableGen/CodeGenTarget.h
@@ -71,7 +71,7 @@ class CodeGenTarget {
void ReadInstructions() const;
void ReadLegalValueTypes() const;
- std::vector<const CodeGenInstruction*> InstrsByEnum;
+ mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
public:
CodeGenTarget();
@@ -205,25 +205,25 @@ public:
CodeGenInstruction &getInstruction(const Record *InstRec) const;
- typedef std::map<std::string,
- CodeGenInstruction>::const_iterator inst_iterator;
- inst_iterator inst_begin() const { return getInstructions().begin(); }
- inst_iterator inst_end() const { return Instructions.end(); }
-
/// getInstructionsByEnumValue - Return all of the instructions defined by the
/// target, ordered by their enum value.
- const std::vector<const CodeGenInstruction*> &getInstructionsByEnumValue() {
+ const std::vector<const CodeGenInstruction*> &
+ getInstructionsByEnumValue() const {
if (InstrsByEnum.empty()) ComputeInstrsByEnum();
return InstrsByEnum;
}
-
+ typedef std::vector<const CodeGenInstruction*>::const_iterator inst_iterator;
+ inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
+ inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
+
+
/// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
///
bool isLittleEndianEncoding() const;
private:
- void ComputeInstrsByEnum();
+ void ComputeInstrsByEnum() const;
};
/// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
diff --git a/utils/TableGen/InstrEnumEmitter.cpp b/utils/TableGen/InstrEnumEmitter.cpp
index 4162107bce..47a8474c35 100644
--- a/utils/TableGen/InstrEnumEmitter.cpp
+++ b/utils/TableGen/InstrEnumEmitter.cpp
@@ -26,14 +26,7 @@ void InstrEnumEmitter::run(raw_ostream &OS) {
CodeGenTarget Target;
// We must emit the PHI opcode first...
- std::string Namespace;
- for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
- E = Target.inst_end(); II != E; ++II) {
- if (II->second.Namespace != "TargetOpcode") {
- Namespace = II->second.Namespace;
- break;
- }
- }
+ std::string Namespace = Target.getInstNamespace();
if (Namespace.empty()) {
fprintf(stderr, "No instructions defined!\n");
diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index 83602bb65c..72c4e73ca1 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -149,7 +149,7 @@ void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
const CodeGenTarget &Target = CDP.getTargetInfo();
for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
E = Target.inst_end(); II != E; ++II) {
- std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
+ std::vector<std::string> OperandInfo = GetOperandInfo(**II);
unsigned &N = OperandInfoIDs[OperandInfo];
if (N != 0) continue;
@@ -214,7 +214,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
// Emit all of the instruction's implicit uses and defs.
for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
E = Target.inst_end(); II != E; ++II) {
- Record *Inst = II->second.TheDef;
+ Record *Inst = (*II)->TheDef;
std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
if (!Uses.empty()) {
unsigned &IL = EmittedLists[Uses];