Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 21 insertions, 6 deletions

diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index a3647c1f0e..617a873cac 100644
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -233,7 +233,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
                      (Name.find("CRC32") != Name.npos);
   HasFROperands    = hasFROperands();
   HasVEX_LPrefix   = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
-  
+
   // Check for 64-bit inst which does not require REX
   Is32Bit = false;
   Is64Bit = false;
@@ -265,6 +265,9 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
              Rec->getName().find("PUSH64") != Name.npos ||
              Rec->getName().find("POP64") != Name.npos;
 
+  // FIXME: BEXTR uses VEX.vvvv to encode its third operand
+  IsBEXTR = Rec->getName().find("BEXTR") != Name.npos;
+
   ShouldBeEmitted  = true;
 }
   
@@ -695,13 +698,18 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
              "Unexpected number of operands for MRMSrcRegFrm");
   
     HANDLE_OPERAND(roRegister)
-       
-    if (HasVEX_4VPrefix)
+
+    if (HasVEX_4VPrefix && !IsBEXTR)
       // FIXME: In AVX, the register below becomes the one encoded
       // in ModRMVEX and the one above the one in the VEX.VVVV field
       HANDLE_OPERAND(vvvvRegister)
-          
+
     HANDLE_OPERAND(rmRegister)
+
+    // FIXME: BEXTR uses VEX.vvvv for Operand 3
+    if (IsBEXTR)
+      HANDLE_OPERAND(vvvvRegister)
+
     HANDLE_OPTIONAL(immediate)
     break;
   case X86Local::MRMSrcMem:
@@ -719,12 +727,17 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
     
     HANDLE_OPERAND(roRegister)
 
-    if (HasVEX_4VPrefix)
+    if (HasVEX_4VPrefix && !IsBEXTR)
       // FIXME: In AVX, the register below becomes the one encoded
       // in ModRMVEX and the one above the one in the VEX.VVVV field
       HANDLE_OPERAND(vvvvRegister)
 
     HANDLE_OPERAND(memory)
+
+    // FIXME: BEXTR uses VEX.vvvv for Operand 3
+    if (IsBEXTR)
+      HANDLE_OPERAND(vvvvRegister)
+
     HANDLE_OPTIONAL(immediate)
     break;
   case X86Local::MRM0r:
diff --git a/utils/TableGen/X86RecognizableInstr.h b/utils/TableGen/X86RecognizableInstr.h
index 4441597827..7ed820b80d 100644
--- a/utils/TableGen/X86RecognizableInstr.h
+++ b/utils/TableGen/X86RecognizableInstr.h
@@ -70,7 +70,9 @@ private:
   bool Is64Bit;
   // Whether the instruction has the predicate "In32BitMode"
   bool Is32Bit;
-  
+  // Whether the instruction is BEXTR
+  bool IsBEXTR;
+
   /// The instruction name as listed in the tables
   std::string Name;
   /// The AT&T AsmString for the instruction