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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-08-11 23:08:22 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-08-11 23:08:22 +0000 |
| commit | d29583bd32eb3e918b797849f55c0ad2667396c4 (patch) | |
| tree | 339588fc6462cbf8e92bdfd572166e2416cfebc0 /utils/TableGen | |
| parent | cf6abd248672486bf037c8b74d4a779be6d5688a (diff) | |
Fix <rdar://problem/8282498> even if it doesn't reproduce on trunk.
When a register is defined by a partial load:
%reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234
That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.
This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110874 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen')
0 files changed, 0 insertions, 0 deletions