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| author | Craig Topper <craig.topper@gmail.com> | 2012-09-19 06:37:45 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-09-19 06:37:45 +0000 |
| commit | 8a312fb3aaec90537d434a5cc41edf566ff80dca (patch) | |
| tree | 9e96e3d182ef24c7f7db5e1b511d6916a2682b2c /utils/TableGen/X86RecognizableInstr.cpp | |
| parent | f7876426f002d7dd763aff7f16a6e8bfa24599bb (diff) | |
Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164204 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/X86RecognizableInstr.cpp')
| -rw-r--r-- | utils/TableGen/X86RecognizableInstr.cpp | 16 |
1 files changed, 1 insertions, 15 deletions
diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index 4b12279cdd..24155c0a5a 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -244,7 +244,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) || (Name.find("CRC32") != Name.npos); HasFROperands = hasFROperands(); - HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L"); + HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); // Check for 64-bit inst which does not require REX Is32Bit = false; @@ -479,20 +479,6 @@ bool RecognizableInstr::hasFROperands() const { return false; } -bool RecognizableInstr::has256BitOperands() const { - const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; - unsigned numOperands = OperandList.size(); - - for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { - const std::string &recName = OperandList[operandIndex].Rec->getName(); - - if (!recName.compare("VR256")) { - return true; - } - } - return false; -} - void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, unsigned &physicalOperandIndex, unsigned &numPhysicalOperands, |