diff options
| author | Craig Topper <craig.topper@gmail.com> | 2011-10-16 03:51:13 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2011-10-16 03:51:13 +0000 |
| commit | 17730847d59c919d97f097d46a3fcba1888e5300 (patch) | |
| tree | e953de771db6fdc42842e707c1124c6d462265b9 /utils/TableGen/X86RecognizableInstr.cpp | |
| parent | 4025061b8a31e612af17bd9548b35e1918135291 (diff) | |
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/X86RecognizableInstr.cpp')
| -rw-r--r-- | utils/TableGen/X86RecognizableInstr.cpp | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index a3647c1f0e..617a873cac 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -233,7 +233,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, (Name.find("CRC32") != Name.npos); HasFROperands = hasFROperands(); HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L"); - + // Check for 64-bit inst which does not require REX Is32Bit = false; Is64Bit = false; @@ -265,6 +265,9 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, Rec->getName().find("PUSH64") != Name.npos || Rec->getName().find("POP64") != Name.npos; + // FIXME: BEXTR uses VEX.vvvv to encode its third operand + IsBEXTR = Rec->getName().find("BEXTR") != Name.npos; + ShouldBeEmitted = true; } @@ -695,13 +698,18 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { "Unexpected number of operands for MRMSrcRegFrm"); HANDLE_OPERAND(roRegister) - - if (HasVEX_4VPrefix) + + if (HasVEX_4VPrefix && !IsBEXTR) // FIXME: In AVX, the register below becomes the one encoded // in ModRMVEX and the one above the one in the VEX.VVVV field HANDLE_OPERAND(vvvvRegister) - + HANDLE_OPERAND(rmRegister) + + // FIXME: BEXTR uses VEX.vvvv for Operand 3 + if (IsBEXTR) + HANDLE_OPERAND(vvvvRegister) + HANDLE_OPTIONAL(immediate) break; case X86Local::MRMSrcMem: @@ -719,12 +727,17 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { HANDLE_OPERAND(roRegister) - if (HasVEX_4VPrefix) + if (HasVEX_4VPrefix && !IsBEXTR) // FIXME: In AVX, the register below becomes the one encoded // in ModRMVEX and the one above the one in the VEX.VVVV field HANDLE_OPERAND(vvvvRegister) HANDLE_OPERAND(memory) + + // FIXME: BEXTR uses VEX.vvvv for Operand 3 + if (IsBEXTR) + HANDLE_OPERAND(vvvvRegister) + HANDLE_OPTIONAL(immediate) break; case X86Local::MRM0r: |