aboutsummaryrefslogtreecommitdiff
path: root/utils/TableGen/X86DisassemblerTables.cpp
diff options
context:
space:
mode:
authorCraig Topper <craig.topper@gmail.com>2011-11-06 23:04:08 +0000
committerCraig Topper <craig.topper@gmail.com>2011-11-06 23:04:08 +0000
commitc8eb880a7fb0958a3a048a82c8558beec11f1209 (patch)
treeb78bcb93cbee0801c40e6176ccc83d25b62dd637 /utils/TableGen/X86DisassemblerTables.cpp
parent590853667345d6fb191764b9d0bd2ff13589e3a3 (diff)
More AVX2 instructions and their intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/X86DisassemblerTables.cpp')
-rw-r--r--utils/TableGen/X86DisassemblerTables.cpp7
1 files changed, 6 insertions, 1 deletions
diff --git a/utils/TableGen/X86DisassemblerTables.cpp b/utils/TableGen/X86DisassemblerTables.cpp
index e8c9a48973..61e94521f5 100644
--- a/utils/TableGen/X86DisassemblerTables.cpp
+++ b/utils/TableGen/X86DisassemblerTables.cpp
@@ -95,7 +95,10 @@ static inline bool inheritsFrom(InstructionContext child,
case IC_VEX_L:
case IC_VEX_L_XS:
case IC_VEX_L_XD:
+ return false;
case IC_VEX_L_OPSIZE:
+ return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
+ case IC_VEX_L_W_OPSIZE:
return false;
default:
llvm_unreachable("Unknown instruction class");
@@ -494,7 +497,9 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const {
for (index = 0; index < 256; ++index) {
o.indent(i * 2);
- if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
+ if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
+ o << "IC_VEX_L_W_OPSIZE";
+ else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
o << "IC_VEX_L_OPSIZE";
else if ((index & ATTR_VEXL) && (index & ATTR_XD))
o << "IC_VEX_L_XD";