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authorCraig Topper <craig.topper@gmail.com>2011-09-23 06:57:25 +0000
committerCraig Topper <craig.topper@gmail.com>2011-09-23 06:57:25 +0000
commit4da632e6e09b96db4b3f9202cde4e6ca732001c1 (patch)
tree2b2c73074cefca6d6e072e2615db00e10753fd93 /utils/TableGen/X86DisassemblerTables.cpp
parentaaa9fc2e375ac92c9ff0cff5265c79045affe8ba (diff)
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/X86DisassemblerTables.cpp')
-rw-r--r--utils/TableGen/X86DisassemblerTables.cpp6
1 files changed, 5 insertions, 1 deletions
diff --git a/utils/TableGen/X86DisassemblerTables.cpp b/utils/TableGen/X86DisassemblerTables.cpp
index aed27279a5..b12660eea2 100644
--- a/utils/TableGen/X86DisassemblerTables.cpp
+++ b/utils/TableGen/X86DisassemblerTables.cpp
@@ -642,12 +642,16 @@ void DisassemblerTables::setTableFields(OpcodeType type,
InstructionContext insnContext,
uint8_t opcode,
const ModRMFilter &filter,
- InstrUID uid) {
+ InstrUID uid,
+ bool is32bit) {
unsigned index;
ContextDecision &decision = *Tables[type];
for (index = 0; index < IC_max; ++index) {
+ if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
+ continue;
+
if (inheritsFrom((InstructionContext)index,
InstructionSpecifiers[uid].insnContext))
setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],