Starting to refactor Target to separate out code that's needed to fully describe

target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 12 insertions, 8 deletions

diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index 39fe9934cd..b11ef6f698 100644
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -54,7 +54,7 @@ using namespace llvm;
 enum ActionType {
   PrintRecords,
   GenEmitter,
-  GenRegisterEnums, GenRegister, GenRegisterHeader,
+  GenRegisterEnums, GenRegisterDesc, GenRegisterInfo, GenRegisterInfoHeader,
   GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
   GenARMDecoder,
   GenDisassembler,
@@ -95,10 +95,12 @@ namespace {
                                "Generate machine code emitter"),
                     clEnumValN(GenRegisterEnums, "gen-register-enums",
                                "Generate enum values for registers"),
-                    clEnumValN(GenRegister, "gen-register-desc",
-                               "Generate a register info description"),
-                    clEnumValN(GenRegisterHeader, "gen-register-desc-header",
-                               "Generate a register info description header"),
+                    clEnumValN(GenRegisterDesc, "gen-register-desc",
+                               "Generate register descriptions"),
+                    clEnumValN(GenRegisterInfo, "gen-register-info",
+                               "Generate registers & reg-classes info"),
+                    clEnumValN(GenRegisterInfoHeader, "gen-register-info-header",
+                               "Generate registers & reg-classes info header"),
                     clEnumValN(GenInstrEnums, "gen-instr-enums",
                                "Generate enum values for instructions"),
                     clEnumValN(GenInstrs, "gen-instr-desc",
@@ -261,14 +263,16 @@ int main(int argc, char **argv) {
     case GenEmitter:
       CodeEmitterGen(Records).run(Out.os());
       break;
-
     case GenRegisterEnums:
       RegisterInfoEmitter(Records).runEnums(Out.os());
       break;
-    case GenRegister:
+    case GenRegisterDesc:
+      RegisterInfoEmitter(Records).runDesc(Out.os());
+      break;
+    case GenRegisterInfo:
       RegisterInfoEmitter(Records).run(Out.os());
       break;
-    case GenRegisterHeader:
+    case GenRegisterInfoHeader:
       RegisterInfoEmitter(Records).runHeader(Out.os());
       break;
     case GenInstrEnums: