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authorChris Lattner <sabre@nondot.org>2010-03-27 19:15:02 +0000
committerChris Lattner <sabre@nondot.org>2010-03-27 19:15:02 +0000
commit0be6fe71390c50b211beb70e6c50e5fae060f746 (patch)
treed84975ad1b03dbb3f1607b9eebefcde07e980fad /utils/TableGen/DAGISelMatcherGen.cpp
parenta6f8693385636b18ae05e30f5017393ad1309bb2 (diff)
continue pushing tblgen's support for nodes with multiple
results forward. We can now handle an instruction that produces one implicit def and one result instead of one or the other when not at the root of the pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99725 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/DAGISelMatcherGen.cpp')
-rw-r--r--utils/TableGen/DAGISelMatcherGen.cpp25
1 files changed, 17 insertions, 8 deletions
diff --git a/utils/TableGen/DAGISelMatcherGen.cpp b/utils/TableGen/DAGISelMatcherGen.cpp
index fda1d457b9..f7fd493cd3 100644
--- a/utils/TableGen/DAGISelMatcherGen.cpp
+++ b/utils/TableGen/DAGISelMatcherGen.cpp
@@ -687,9 +687,19 @@ EmitResultInstructionAsOperand(const TreePatternNode *N,
continue;
}
+ const TreePatternNode *Child = N->getChild(ChildNo);
+
// Otherwise this is a normal operand or a predicate operand without
// 'execute always'; emit it.
- EmitResultOperand(N->getChild(ChildNo), InstOps);
+ unsigned BeforeAddingNumOps = InstOps.size();
+ EmitResultOperand(Child, InstOps);
+ assert(InstOps.size() > BeforeAddingNumOps && "Didn't add any operands");
+
+ // If the operand is an instruction and it produced multiple results, just
+ // take the first one.
+ if (!Child->isLeaf() && Child->getOperator()->isSubClassOf("Instruction"))
+ InstOps.resize(BeforeAddingNumOps+1);
+
++ChildNo;
}
@@ -711,12 +721,8 @@ EmitResultInstructionAsOperand(const TreePatternNode *N,
// Determine the result types.
SmallVector<MVT::SimpleValueType, 4> ResultVTs;
- if (N->getNumTypes()) {
- // FIXME2: If the node has multiple results, we should add them. For now,
- // preserve existing behavior?!
- assert(N->getNumTypes() == 1);
- ResultVTs.push_back(N->getType(0));
- }
+ for (unsigned i = 0, e = N->getNumTypes(); i != e; ++i)
+ ResultVTs.push_back(N->getType(i));
// If this is the root instruction of a pattern that has physical registers in
// its result pattern, add output VTs for them. For example, X86 has:
@@ -727,7 +733,7 @@ EmitResultInstructionAsOperand(const TreePatternNode *N,
// If the root came from an implicit def in the instruction handling stuff,
// don't re-add it.
Record *HandledReg = 0;
- if (NumResults == 0 && N->getNumTypes() != 0 &&
+ if (N->getNumTypes() != 0 &&
!II.ImplicitDefs.empty())
HandledReg = II.ImplicitDefs[0];
@@ -762,6 +768,9 @@ EmitResultInstructionAsOperand(const TreePatternNode *N,
bool NodeHasMemRefs =
isRoot && Pattern.getSrcPattern()->TreeHasProperty(SDNPMemOperand, CGP);
+ assert((!ResultVTs.empty() || TreeHasOutFlag || NodeHasChain) &&
+ "Node has no result");
+
AddMatcher(new EmitNodeMatcher(II.Namespace+"::"+II.TheDef->getName(),
ResultVTs.data(), ResultVTs.size(),
InstOps.data(), InstOps.size(),