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author | Jyotsna Verma <jverma@codeaurora.org> | 2013-03-01 17:37:13 +0000 |
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committer | Jyotsna Verma <jverma@codeaurora.org> | 2013-03-01 17:37:13 +0000 |
commit | ef94c6c85eed42d16fde51ee4415d27bb281a2ca (patch) | |
tree | 22a49c445983c67f187242e481d6f02b4afe4093 /test | |
parent | ae1dbb39f7f769ac83ec2ec6a6c243c26c2aba02 (diff) |
Hexagon: Add constant extender support framework.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176358 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/Hexagon/cext-valid-packet1.ll | 18 | ||||
-rw-r--r-- | test/CodeGen/Hexagon/cext-valid-packet2.ll | 43 |
2 files changed, 61 insertions, 0 deletions
diff --git a/test/CodeGen/Hexagon/cext-valid-packet1.ll b/test/CodeGen/Hexagon/cext-valid-packet1.ll new file mode 100644 index 0000000000..a479d37e4a --- /dev/null +++ b/test/CodeGen/Hexagon/cext-valid-packet1.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s + +; Check that the packetizer generates valid packets with constant +; extended instructions. +; CHECK: { +; CHECK-NEXT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}, ##{{[0-9]+}}) +; CHECK-NEXT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}, ##{{[0-9]+}}) +; CHECK-NEXT: } + +define i32 @check-packet1(i32 %a, i32 %b, i32 %c) nounwind readnone { +entry: + %add = add nsw i32 %a, 200000 + %add1 = add nsw i32 %b, 200001 + %add2 = add nsw i32 %c, 200002 + %cmp = icmp sgt i32 %add, %add1 + %b.addr.0 = select i1 %cmp, i32 %add1, i32 %add2 + ret i32 %b.addr.0 +} diff --git a/test/CodeGen/Hexagon/cext-valid-packet2.ll b/test/CodeGen/Hexagon/cext-valid-packet2.ll new file mode 100644 index 0000000000..2788a6b1c8 --- /dev/null +++ b/test/CodeGen/Hexagon/cext-valid-packet2.ll @@ -0,0 +1,43 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; Check that the packetizer generates valid packets with constant +; extended add and base+offset store instructions. + +; CHECK: { +; CHECK-NEXT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}, ##{{[0-9]+}}) +; CHECK-NEXT: memw(r{{[0-9]+}}+{{ *}}##{{[0-9]+}}){{ *}}={{ *}}r{{[0-9]+}}.new +; CHECK-NEXT: } + +define i32 @test(i32* nocapture %a, i32* nocapture %b, i32 %c) nounwind { +entry: + %add = add nsw i32 %c, 200002 + %0 = load i32* %a, align 4 + %add1 = add nsw i32 %0, 200000 + %arrayidx2 = getelementptr inbounds i32* %a, i32 3000 + store i32 %add1, i32* %arrayidx2, align 4 + %1 = load i32* %b, align 4 + %add4 = add nsw i32 %1, 200001 + %arrayidx5 = getelementptr inbounds i32* %a, i32 1 + store i32 %add4, i32* %arrayidx5, align 4 + %arrayidx7 = getelementptr inbounds i32* %b, i32 1 + %2 = load i32* %arrayidx7, align 4 + %cmp = icmp sgt i32 %add4, %2 + br i1 %cmp, label %if.then, label %if.else + +if.then: ; preds = %entry + %arrayidx8 = getelementptr inbounds i32* %a, i32 2 + %3 = load i32* %arrayidx8, align 4 + %arrayidx9 = getelementptr inbounds i32* %b, i32 2000 + %4 = load i32* %arrayidx9, align 4 + %sub = sub nsw i32 %3, %4 + %arrayidx10 = getelementptr inbounds i32* %a, i32 4000 + store i32 %sub, i32* %arrayidx10, align 4 + br label %if.end + +if.else: ; preds = %entry + %arrayidx11 = getelementptr inbounds i32* %b, i32 3200 + store i32 %add, i32* %arrayidx11, align 4 + br label %if.end + +if.end: ; preds = %if.else, %if.then + ret i32 %add +} |