diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2012-11-12 14:50:59 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-11-12 14:50:59 +0000 |
| commit | 8b9796f4f83bea2bbefcd2822eb574abdb7f3d1b (patch) | |
| tree | d4c612832e01d18da7a74a73a609571c378d1af7 /test/Transforms/BBVectorize | |
| parent | dece7039dd40eea928ec10abc1e310a846b68dd7 (diff) | |
BBVectorize: Check the input types of shuffles for legality
This fixes a bug where shuffles were being fused such that the
resulting input types were not legal on the target. This would
occur only when both inputs and dependencies were also foldable
operations (such as other shuffles) and there were other connected
pairs in the same block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167731 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Transforms/BBVectorize')
| -rw-r--r-- | test/Transforms/BBVectorize/X86/sh-types.ll | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/test/Transforms/BBVectorize/X86/sh-types.ll b/test/Transforms/BBVectorize/X86/sh-types.ll new file mode 100644 index 0000000000..0bcb714d5e --- /dev/null +++ b/test/Transforms/BBVectorize/X86/sh-types.ll @@ -0,0 +1,25 @@ +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -bb-vectorize -S | FileCheck %s + +define <4 x float> @test7(<4 x float> %A1, <4 x float> %B1, double %C1, double %C2, double %D1, double %D2) { + %A2 = shufflevector <4 x float> %A1, <4 x float> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3> + %B2 = shufflevector <4 x float> %B1, <4 x float> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3> + %X1 = shufflevector <4 x float> %A2, <4 x float> undef, <2 x i32> <i32 0, i32 1> + %X2 = shufflevector <4 x float> %B2, <4 x float> undef, <2 x i32> <i32 2, i32 3> + %Y1 = shufflevector <2 x float> %X1, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> + %Y2 = shufflevector <2 x float> %X2, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> + + %M1 = fsub double %C1, %D1 + %M2 = fsub double %C2, %D2 + %N1 = fmul double %M1, %C1 + %N2 = fmul double %M2, %C2 + %Z1 = fadd double %N1, %D1 + %Z2 = fadd double %N2, %D2 + + %R = fmul <4 x float> %Y1, %Y2 + ret <4 x float> %R +; CHECK: @test7 +; CHECK-NOT: <8 x float> +; CHECK: ret <4 x float> +} + |