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| author | Joel Jones <joel_k_jones@apple.com> | 2013-02-14 23:18:40 +0000 |
|---|---|---|
| committer | Joel Jones <joel_k_jones@apple.com> | 2013-02-14 23:18:40 +0000 |
| commit | 48e841d41c57712f4d6a94b1123f198bdf0bda7d (patch) | |
| tree | a0aae726441b6bfda2bf71c799dd269581464474 /test/MC/ARM | |
| parent | d6f19c716378bce0acc3cbfc9dc9297468f046a0 (diff) | |
The ARM NEON vector compare instructions take three arguments. However, the
assembler should also accept a two arg form, as the docuemntation specifies that
the first (destination) register is optional.
This patch uses TwoOperandAliasConstraint to add the two argument form.
It also fixes an 80-column formatting problem in:
test/MC/ARM/neon-bitwise-encoding
<rdar://problem/12909419> Clang rejects ARM NEON assembly instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175221 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/ARM')
| -rw-r--r-- | test/MC/ARM/neon-bitwise-encoding.s | 68 |
1 files changed, 67 insertions, 1 deletions
diff --git a/test/MC/ARM/neon-bitwise-encoding.s b/test/MC/ARM/neon-bitwise-encoding.s index e8c1dd6348..8c7228835c 100644 --- a/test/MC/ARM/neon-bitwise-encoding.s +++ b/test/MC/ARM/neon-bitwise-encoding.s @@ -1,4 +1,5 @@ -@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s \ +@ RUN: | FileCheck %s vand d16, d17, d16 vand q8, q8, q9 @@ -255,6 +256,42 @@ veor.f q8, q2 veor.i64 q8, q2 + vclt.s16 q5, #0 + vclt.s16 d5, #0 + + vceq.s16 q5, q3 + vceq.s16 d5, d3 + + vcgt.s16 q5, q3 + vcgt.s16 d5, d3 + + vcge.s16 q5, q3 + vcge.s16 d5, d3 + + vcgt.s16 q5, #0 + vcgt.s16 d5, #0 + + vcge.s16 q5, #0 + vcge.s16 d5, #0 + + vceq.s16 q5, #0 + vceq.s16 d5, #0 + + vcle.s16 q5, #0 + vcle.s16 d5, #0 + + vacge.f32 d5, d30 + vacge.f32 q5, q3 + + vacgt.f32 d5, d30 + vacgt.f32 q5, q3 + +@ FIXME: We don't have an alias that reverses the operands +@ vacle.f32 d5, d30 +@ vacle.f32 q5, q3 +@ vaclt.f32 d5, d30 +@ vaclt.f32 q5, q3 + @ CHECK: vand q6, q6, q5 @ encoding: [0x5a,0xc1,0x0c,0xf2] @ CHECK: vand q6, q6, q5 @ encoding: [0x5a,0xc1,0x0c,0xf2] @ CHECK: vand q7, q7, q1 @ encoding: [0x52,0xe1,0x0e,0xf2] @@ -272,3 +309,32 @@ @ CHECK: veor q7, q7, q1 @ encoding: [0x52,0xe1,0x0e,0xf3] @ CHECK: veor q8, q8, q2 @ encoding: [0xd4,0x01,0x40,0xf3] @ CHECK: veor q8, q8, q2 @ encoding: [0xd4,0x01,0x40,0xf3] +@ CHECK: vclt.s16 q5, q5, #0 @ encoding: [0x4a,0xa2,0xb5,0xf3] +@ CHECK: vclt.s16 d5, d5, #0 @ encoding: [0x05,0x52,0xb5,0xf3] + +@ CHECK: vceq.i16 q5, q5, q3 @ encoding: [0x56,0xa8,0x1a,0xf3] +@ CHECK: vceq.i16 d5, d5, d3 @ encoding: [0x13,0x58,0x15,0xf3] + +@ CHECK: vcgt.s16 q5, q5, q3 @ encoding: [0x46,0xa3,0x1a,0xf2] +@ CHECK: vcgt.s16 d5, d5, d3 @ encoding: [0x03,0x53,0x15,0xf2] + +@ CHECK: vcge.s16 q5, q5, q3 @ encoding: [0x56,0xa3,0x1a,0xf2] +@ CHECK: vcge.s16 d5, d5, d3 @ encoding: [0x13,0x53,0x15,0xf2] + +@ CHECK: vcgt.s16 q5, q5, #0 @ encoding: [0x4a,0xa0,0xb5,0xf3] +@ CHECK: vcgt.s16 d5, d5, #0 @ encoding: [0x05,0x50,0xb5,0xf3] + +@ CHECK: vcge.s16 q5, q5, #0 @ encoding: [0xca,0xa0,0xb5,0xf3] +@ CHECK: vcge.s16 d5, d5, #0 @ encoding: [0x85,0x50,0xb5,0xf3] + +@ CHECK: vceq.i16 q5, q5, #0 @ encoding: [0x4a,0xa1,0xb5,0xf3] +@ CHECK: vceq.i16 d5, d5, #0 @ encoding: [0x05,0x51,0xb5,0xf3] + +@ CHECK: vcle.s16 q5, q5, #0 @ encoding: [0xca,0xa1,0xb5,0xf3] +@ CHECK: vcle.s16 d5, d5, #0 @ encoding: [0x85,0x51,0xb5,0xf3] + +@ CHECK: vacge.f32 d5, d5, d30 @ encoding: [0x3e,0x5e,0x05,0xf3] +@ CHECK: vacge.f32 q5, q5, q3 @ encoding: [0x56,0xae,0x0a,0xf3] + +@ CHECK: vacgt.f32 d5, d5, d30 @ encoding: [0x3e,0x5e,0x25,0xf3] +@ CHECK: vacgt.f32 q5, q5, q3 @ encoding: [0x56,0xae,0x2a,0xf3] |