diff options
| author | Nadav Rotem <nrotem@apple.com> | 2013-01-05 05:42:48 +0000 |
|---|---|---|
| committer | Nadav Rotem <nrotem@apple.com> | 2013-01-05 05:42:48 +0000 |
| commit | 5d1f5c17377e56d88a525cf82d02e6e5df254580 (patch) | |
| tree | a9198bd8746793423ea59187b1a108dea0852805 /test/CodeGen/X86/select.ll | |
| parent | 255cd6f317f3a0bad6e7939ca5ce49b33c6676f9 (diff) | |
Revert revision 171524. Original message:
URL: http://llvm.org/viewvc/llvm-project?rev=171524&view=rev
Log:
The current Intel Atom microarchitecture has a feature whereby when a function
returns early then it is slightly faster to execute a sequence of NOP
instructions to wait until the return address is ready,
as opposed to simply stalling on the ret instruction
until the return address is ready.
When compiling for X86 Atom only, this patch will run a pass, called
"X86PadShortFunction" which will add NOP instructions where less than four
cycles elapse between function entry and return.
It includes tests.
Patch by Andy Zhang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171603 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/X86/select.ll')
| -rw-r--r-- | test/CodeGen/X86/select.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/CodeGen/X86/select.ll b/test/CodeGen/X86/select.ll index 09ca07b31a..3bec3acdbf 100644 --- a/test/CodeGen/X86/select.ll +++ b/test/CodeGen/X86/select.ll @@ -282,7 +282,7 @@ define i32 @test13(i32 %a, i32 %b) nounwind { ; ATOM: test13: ; ATOM: cmpl ; ATOM-NEXT: sbbl -; ATOM: ret +; ATOM-NEXT: ret } define i32 @test14(i32 %a, i32 %b) nounwind { @@ -299,7 +299,7 @@ define i32 @test14(i32 %a, i32 %b) nounwind { ; ATOM: cmpl ; ATOM-NEXT: sbbl ; ATOM-NEXT: notl -; ATOM: ret +; ATOM-NEXT: ret } ; rdar://10961709 |