Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139400 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 38 insertions, 0 deletions

diff --git a/test/CodeGen/X86/avx-blend.ll b/test/CodeGen/X86/avx-blend.ll
index dc0d013698..e025e26bde 100644
--- a/test/CodeGen/X86/avx-blend.ll
+++ b/test/CodeGen/X86/avx-blend.ll
@@ -1,5 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -promote-elements -mattr=+avx | FileCheck %s
 
+; AVX128 tests:
+
 ;CHECK: vsel_float
 ;CHECK: vblendvps
 ;CHECK: ret
@@ -45,3 +47,39 @@ define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
 }
 
 
+; AVX256 tests:
+
+
+;CHECK: vsel_float
+;CHECK: vblendvps
+;CHECK: ret
+define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
+  %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x float> %v1, <8 x float> %v2
+  ret <8 x float> %vsel
+}
+
+;CHECK: vsel_i32
+;CHECK: vblendvps
+;CHECK: ret
+define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
+  %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i32> %v1, <8 x i32> %v2
+  ret <8 x i32> %vsel
+}
+
+;CHECK: vsel_double
+;CHECK: vblendvpd
+;CHECK: ret
+define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
+  %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x double> %v1, <8 x double> %v2
+  ret <8 x double> %vsel
+}
+
+;CHECK: vsel_i64
+;CHECK: vblendvpd
+;CHECK: ret
+define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
+  %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i64> %v1, <8 x i64> %v2
+  ret <8 x i64> %vsel
+}
+
+