diff options
| author | Michel Danzer <michel.daenzer@amd.com> | 2013-02-14 07:43:51 +0000 |
|---|---|---|
| committer | Michel Danzer <michel.daenzer@amd.com> | 2013-02-14 07:43:51 +0000 |
| commit | d4addbe78a344a1b23a8885aa5490e706aa16064 (patch) | |
| tree | 3f8d5d114956124a0d74574c36e658afaf3d298d /test/CodeGen/R600/llvm.SI.sample.ll | |
| parent | 05fdb825358176def129e18abd37f4791c14c780 (diff) | |
R600: Add lit tests for texture sampling instruction selection.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175138 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/llvm.SI.sample.ll')
| -rw-r--r-- | test/CodeGen/R600/llvm.SI.sample.ll | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/test/CodeGen/R600/llvm.SI.sample.ll b/test/CodeGen/R600/llvm.SI.sample.ll new file mode 100644 index 0000000000..34d19358f8 --- /dev/null +++ b/test/CodeGen/R600/llvm.SI.sample.ll @@ -0,0 +1,71 @@ +;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s + +;CHECK: IMAGE_SAMPLE +;CHECK-NEXT: S_WAITCNT 1792 +;CHECK-NEXT: IMAGE_SAMPLE +;CHECK-NEXT: S_WAITCNT 1792 +;CHECK-NEXT: IMAGE_SAMPLE +;CHECK-NEXT: S_WAITCNT 1792 +;CHECK-NEXT: IMAGE_SAMPLE +;CHECK-NEXT: S_WAITCNT 1792 +;CHECK-NEXT: IMAGE_SAMPLE +;CHECK-NEXT: S_WAITCNT 1792 +;CHECK-NEXT: IMAGE_SAMPLE_C +;CHECK-NEXT: S_WAITCNT 1792 +;CHECK-NEXT: IMAGE_SAMPLE_C +;CHECK-NEXT: S_WAITCNT 1792 +;CHECK-NEXT: IMAGE_SAMPLE_C +;CHECK-NEXT: S_WAITCNT 1792 +;CHECK-NEXT: IMAGE_SAMPLE +;CHECK-NEXT: S_WAITCNT 1792 +;CHECK-NEXT: IMAGE_SAMPLE +;CHECK-NEXT: S_WAITCNT 1792 +;CHECK-NEXT: IMAGE_SAMPLE_C +;CHECK-NEXT: S_WAITCNT 1792 +;CHECK-NEXT: IMAGE_SAMPLE_C +;CHECK-NEXT: S_WAITCNT 1792 +;CHECK-NEXT: IMAGE_SAMPLE_C +;CHECK-NEXT: S_WAITCNT 1792 +;CHECK-NEXT: IMAGE_SAMPLE +;CHECK-NEXT: S_WAITCNT 1792 +;CHECK-NEXT: IMAGE_SAMPLE +;CHECK-NEXT: S_WAITCNT 1792 +;CHECK-NEXT: IMAGE_SAMPLE + +define void @test() { + %res1 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + <8 x i32> undef, <4 x i32> undef, i32 1) + %res2 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + <8 x i32> undef, <4 x i32> undef, i32 2) + %res3 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + <8 x i32> undef, <4 x i32> undef, i32 3) + %res4 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + <8 x i32> undef, <4 x i32> undef, i32 4) + %res5 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + <8 x i32> undef, <4 x i32> undef, i32 5) + %res6 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + <8 x i32> undef, <4 x i32> undef, i32 6) + %res7 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + <8 x i32> undef, <4 x i32> undef, i32 7) + %res8 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + <8 x i32> undef, <4 x i32> undef, i32 8) + %res9 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + <8 x i32> undef, <4 x i32> undef, i32 9) + %res10 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + <8 x i32> undef, <4 x i32> undef, i32 10) + %res11 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + <8 x i32> undef, <4 x i32> undef, i32 11) + %res12 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + <8 x i32> undef, <4 x i32> undef, i32 12) + %res13 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + <8 x i32> undef, <4 x i32> undef, i32 13) + %res14 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + <8 x i32> undef, <4 x i32> undef, i32 14) + %res15 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + <8 x i32> undef, <4 x i32> undef, i32 15) + %res16 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + <8 x i32> undef, <4 x i32> undef, i32 16) + ret void +} + +declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32) |