diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2013-04-01 17:52:07 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-04-01 17:52:07 +0000 |
| commit | 46479197843ecb651adc9417c49bbd1b00acfcb6 (patch) | |
| tree | 143df888333c2baabf6cf07c8ef7297b86b5035c /test/CodeGen/PowerPC/i32-to-float.ll | |
| parent | a1f4290ac94f34173e3561c717390de07dccc646 (diff) | |
Add more PPC floating-point conversion instructions
The P7 and A2 have additional floating-point conversion instructions which
allow a direct two-instruction sequence (plus load/store) to convert from all
combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores,
only some combinations were directly available).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178480 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/i32-to-float.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/i32-to-float.ll | 41 |
1 files changed, 39 insertions, 2 deletions
diff --git a/test/CodeGen/PowerPC/i32-to-float.ll b/test/CodeGen/PowerPC/i32-to-float.ll index bed940c5de..2707d0352d 100644 --- a/test/CodeGen/PowerPC/i32-to-float.ll +++ b/test/CodeGen/PowerPC/i32-to-float.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 | FileCheck -check-prefix=CHECK-PWR6 %s ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck -check-prefix=CHECK-A2 %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -16,11 +17,17 @@ entry: ; CHECK: frsp 1, [[REG3]] ; CHECK: blr +; CHECK-PWR6: @foo +; CHECK-PWR6: stw 3, +; CHECK-PWR6: lfiwax [[REG:[0-9]+]], +; CHECK-PWR6: fcfid [[REG2:[0-9]+]], [[REG]] +; CHECK-PWR6: frsp 1, [[REG2]] +; CHECK-PWR6: blr + ; CHECK-A2: @foo ; CHECK-A2: stw 3, ; CHECK-A2: lfiwax [[REG:[0-9]+]], -; CHECK-A2: fcfid [[REG2:[0-9]+]], [[REG]] -; CHECK-A2: frsp 1, [[REG2]] +; CHECK-A2: fcfids 1, [[REG]] ; CHECK-A2: blr } @@ -36,6 +43,12 @@ entry: ; CHECK: fcfid 1, [[REG2]] ; CHECK: blr +; CHECK-PWR6: @goo +; CHECK-PWR6: stw 3, +; CHECK-PWR6: lfiwax [[REG:[0-9]+]], +; CHECK-PWR6: fcfid 1, [[REG]] +; CHECK-PWR6: blr + ; CHECK-A2: @goo ; CHECK-A2: stw 3, ; CHECK-A2: lfiwax [[REG:[0-9]+]], @@ -43,3 +56,27 @@ entry: ; CHECK-A2: blr } +define float @foou(i32 %a) nounwind { +entry: + %x = uitofp i32 %a to float + ret float %x + +; CHECK-A2: @foou +; CHECK-A2: stw 3, +; CHECK-A2: lfiwzx [[REG:[0-9]+]], +; CHECK-A2: fcfidus 1, [[REG]] +; CHECK-A2: blr +} + +define double @goou(i32 %a) nounwind { +entry: + %x = uitofp i32 %a to double + ret double %x + +; CHECK-A2: @goou +; CHECK-A2: stw 3, +; CHECK-A2: lfiwzx [[REG:[0-9]+]], +; CHECK-A2: fcfidu 1, [[REG]] +; CHECK-A2: blr +} + |