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authorJustin Holewinski <jholewinski@nvidia.com>2013-03-20 00:10:32 +0000
committerJustin Holewinski <jholewinski@nvidia.com>2013-03-20 00:10:32 +0000
commitd73dc544f5e37e6d58befc71e57da3c132804543 (patch)
tree36c6db5ed73b78c591cf873be430a17f49f8f3fa /test/CodeGen/NVPTX/sched2.ll
parent580f9c85fd7a3c90884ed7ee7c2d613923a53bb3 (diff)
Propagate DAG node ordering during type legalization and instruction selection
A node's ordering is only propagated during legalization if (a) the new node does not have an ordering (is not a CSE'd node), or (b) the new node has an ordering that is higher than the node being legalized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177465 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/NVPTX/sched2.ll')
-rw-r--r--test/CodeGen/NVPTX/sched2.ll32
1 files changed, 32 insertions, 0 deletions
diff --git a/test/CodeGen/NVPTX/sched2.ll b/test/CodeGen/NVPTX/sched2.ll
new file mode 100644
index 0000000000..71a9a4963f
--- /dev/null
+++ b/test/CodeGen/NVPTX/sched2.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+define void @foo(<2 x i32>* %a) {
+; CHECK: .func foo
+; CHECK: ld.v2.u32
+; CHECK-NEXT: ld.v2.u32
+; CHECK-NEXT: ld.v2.u32
+; CHECK-NEXT: ld.v2.u32
+; CHECK-NEXT: add.s32
+; CHECK-NEXT: add.s32
+; CHECK-NEXT: add.s32
+; CHECK-NEXT: add.s32
+; CHECK-NEXT: add.s32
+; CHECK-NEXT: add.s32
+ %ptr0 = getelementptr <2 x i32>* %a, i32 0
+ %val0 = load <2 x i32>* %ptr0
+ %ptr1 = getelementptr <2 x i32>* %a, i32 1
+ %val1 = load <2 x i32>* %ptr1
+ %ptr2 = getelementptr <2 x i32>* %a, i32 2
+ %val2 = load <2 x i32>* %ptr2
+ %ptr3 = getelementptr <2 x i32>* %a, i32 3
+ %val3 = load <2 x i32>* %ptr3
+
+ %t0 = add <2 x i32> %val0, %val1
+ %t1 = add <2 x i32> %t0, %val2
+ %t2 = add <2 x i32> %t1, %val3
+
+ store <2 x i32> %t2, <2 x i32>* %a
+
+ ret void
+}
+