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| author | Akira Hatanaka <ahatanak@gmail.com> | 2011-08-16 03:51:51 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanak@gmail.com> | 2011-08-16 03:51:51 +0000 |
| commit | 614051a1c534aff052152b0162a414b3271e8fca (patch) | |
| tree | 019e11b687f2e95ffdc968669d1f325272883b90 /test/CodeGen/Mips/select.ll | |
| parent | 8957481e6a3a4217499f739bae24401576ade078 (diff) | |
Fix handling of double precision loads and stores when Mips1 is targeted.
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.
Without the changes made in this patch, llc produces code that has the same
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137711 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips/select.ll')
| -rw-r--r-- | test/CodeGen/Mips/select.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/Mips/select.ll b/test/CodeGen/Mips/select.ll index c83fa3ece0..3ea4c4b2e3 100644 --- a/test/CodeGen/Mips/select.ll +++ b/test/CodeGen/Mips/select.ll @@ -25,7 +25,7 @@ entry: define double @sel2_1(i32 %s, double %f0, double %f1) nounwind readnone { entry: ; CHECK-MIPS32R2: movn.d -; CHECK-MIPS1: beq +; CHECK-MIPS1: bne %tobool = icmp ne i32 %s, 0 %cond = select i1 %tobool, double %f0, double %f1 ret double %cond |