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authorJyotsna Verma <jverma@codeaurora.org>2013-03-26 15:43:57 +0000
committerJyotsna Verma <jverma@codeaurora.org>2013-03-26 15:43:57 +0000
commit7bb9585c6e2528e3e4e928e7691dd97a106e3de0 (patch)
tree3c366ccf57799f92645110eca0ceee08b8ea82be /test/CodeGen/Hexagon
parentfdc6177490404b7dac178f24671fb3ea39bae791 (diff)
Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178032 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Hexagon')
-rw-r--r--test/CodeGen/Hexagon/ashift-left-right.ll21
1 files changed, 21 insertions, 0 deletions
diff --git a/test/CodeGen/Hexagon/ashift-left-right.ll b/test/CodeGen/Hexagon/ashift-left-right.ll
new file mode 100644
index 0000000000..7c41bc7bbf
--- /dev/null
+++ b/test/CodeGen/Hexagon/ashift-left-right.ll
@@ -0,0 +1,21 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+
+define i32 @foo(i32 %a, i32 %b) nounwind readnone {
+; CHECK: lsl
+; CHECK: aslh
+entry:
+ %shl1 = shl i32 16, %a
+ %shl2 = shl i32 %b, 16
+ %ret = mul i32 %shl1, %shl2
+ ret i32 %ret
+}
+
+define i32 @bar(i32 %a, i32 %b) nounwind readnone {
+; CHECK: asrh
+; CHECK: lsr
+entry:
+ %shl1 = ashr i32 16, %a
+ %shl2 = ashr i32 %b, 16
+ %ret = mul i32 %shl1, %shl2
+ ret i32 %ret
+}