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| author | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-16 10:02:06 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-16 10:02:06 +0000 |
| commit | c32a8c9073e5aafe9b4c41dddd416d378216758f (patch) | |
| tree | 97c4db56a283742c2b7dc84b4204713b6b7f4cd3 /test/CodeGen/CellSPU | |
| parent | 9cabfa68420fbd202f4fde214b5aa857352da0f3 (diff) | |
Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was
no pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142130 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/CellSPU')
| -rw-r--r-- | test/CodeGen/CellSPU/shift_ops.ll | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/test/CodeGen/CellSPU/shift_ops.ll b/test/CodeGen/CellSPU/shift_ops.ll index 3252c776ec..8ecf15432d 100644 --- a/test/CodeGen/CellSPU/shift_ops.ll +++ b/test/CodeGen/CellSPU/shift_ops.ll @@ -342,3 +342,7 @@ define <8 x i16> @ashr_v8i16(<8 x i16> %val, <8 x i16> %sh) { %rv = ashr <8 x i16> %val, %sh ret <8 x i16> %rv } + +define <2 x i64> @special_const() { + ret <2 x i64> <i64 4294967295, i64 4294967295> +} |