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| author | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-16 20:31:33 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-16 20:31:33 +0000 |
| commit | 8fb06b3e8f7fc92e472e17fecf5ee3ba44fbb6ab (patch) | |
| tree | 0bb4f05809105f8db17e8f199f0627d92cd6f04c /test/CodeGen/ARM/vrev.ll | |
| parent | c4a90c5271de99e682b00986c9ca7cde3e1dde4f (diff) | |
Enable element promotion type legalization by deafault.
Changed tests which assumed that vectors are legalized by widening them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142152 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/vrev.ll')
| -rw-r--r-- | test/CodeGen/ARM/vrev.ll | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/test/CodeGen/ARM/vrev.ll b/test/CodeGen/ARM/vrev.ll index 34acd1678a..5c3c0fca10 100644 --- a/test/CodeGen/ARM/vrev.ll +++ b/test/CodeGen/ARM/vrev.ll @@ -150,9 +150,6 @@ define void @test_with_vcombine(<4 x float>* %v) nounwind { ; vrev <4 x i16> should use VREV32 and not VREV64 define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp { -; CHECK: test_vrev64: -; CHECK: vext.16 -; CHECK: vrev32.16 entry: %0 = bitcast <4 x i16>* %source to <8 x i16>* %tmp2 = load <8 x i16>* %0, align 4 |