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| author | Bob Wilson <bob.wilson@apple.com> | 2009-06-22 23:27:02 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2009-06-22 23:27:02 +0000 |
| commit | 5bafff36c798608a189c517d37527e4a38863071 (patch) | |
| tree | 79bd2abbc5253e6f00db07023cf7d829cbcdee5a /test/CodeGen/ARM/vqdmlsl.ll | |
| parent | 5de83afcdc3f4f0edf8caacba523f5d05ee48048 (diff) | |
Add support for ARM's Advanced SIMD (NEON) instruction set.
This is still a work in progress but most of the NEON instruction set
is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/vqdmlsl.ll')
| -rw-r--r-- | test/CodeGen/ARM/vqdmlsl.ll | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/vqdmlsl.ll b/test/CodeGen/ARM/vqdmlsl.ll new file mode 100644 index 0000000000..2b71ed5563 --- /dev/null +++ b/test/CodeGen/ARM/vqdmlsl.ll @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep {vqdmlsl\\.s16} %t | count 1 +; RUN: grep {vqdmlsl\\.s32} %t | count 1 + +define <4 x i32> @vqdmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = call <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) + ret <4 x i32> %tmp4 +} + +define <2 x i64> @vqdmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) + ret <2 x i64> %tmp4 +} + +declare <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone |