Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 18 insertions, 0 deletions

diff --git a/test/CodeGen/ARM/vector-DAGCombine.ll b/test/CodeGen/ARM/vector-DAGCombine.ll
index 3ab0cfcbbc..81bdc44863 100644
--- a/test/CodeGen/ARM/vector-DAGCombine.ll
+++ b/test/CodeGen/ARM/vector-DAGCombine.ll
@@ -105,3 +105,21 @@ define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind {
   store i64 %t1, i64* %ptr
   ret void
 }
+
+; Test trying to do a AND Combine on illegal types.
+define void @andVec(<3 x i8>* %A) nounwind {
+  %tmp = load <3 x i8>* %A, align 4
+  %and = and <3 x i8> %tmp, <i8 7, i8 7, i8 7>
+  store <3 x i8> %and, <3 x i8>* %A
+  ret void
+}
+
+
+; Test trying to do an OR Combine on illegal types.
+define void @orVec(<3 x i8>* %A) nounwind {
+  %tmp = load <3 x i8>* %A, align 4
+  %or = or <3 x i8> %tmp, <i8 7, i8 7, i8 7>
+  store <3 x i8> %or, <3 x i8>* %A
+  ret void
+}
+