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authorJim Grosbach <grosbach@apple.com>2009-11-15 21:45:34 +0000
committerJim Grosbach <grosbach@apple.com>2009-11-15 21:45:34 +0000
commita44321776ecd96fa0344335d3027758be3386e45 (patch)
tree42736e2f85df41f9651a9b26ed436091643efa5b /test/CodeGen/ARM/spill-q.ll
parent6cb6788b79bcec64886880697fc69b82a296f671 (diff)
Detect need for autoalignment of the stack earlier to catch spills more
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode 6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88874 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/spill-q.ll')
-rw-r--r--test/CodeGen/ARM/spill-q.ll5
1 files changed, 3 insertions, 2 deletions
diff --git a/test/CodeGen/ARM/spill-q.ll b/test/CodeGen/ARM/spill-q.ll
index f4b27a7603..6b44210af7 100644
--- a/test/CodeGen/ARM/spill-q.ll
+++ b/test/CodeGen/ARM/spill-q.ll
@@ -11,8 +11,9 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly
define arm_apcscc void @aaa(%quuz* %this, i8* %block) {
; CHECK: aaa:
-; CHECK: vstmia sp
-; CHECK: vldmia sp
+; CHECK: bic sp, sp, #15
+; CHECK: vst1.64 {{.*}}sp @128
+; CHECK: vld1.64 {{.*}}sp @128
entry:
%0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1]
store float 6.300000e+01, float* undef, align 4