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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-28 06:47:08 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-28 06:47:08 +0000 |
| commit | 7e2fe9150f905167f6685c9730911c2abc08293c (patch) | |
| tree | 4f1798b4cd67ec0d9f7b57e55988c99cd867863f /test/CodeGen/ARM/shifter_operand.ll | |
| parent | 9c3e8e28bd236e95117a25f07d3b466d2db80285 (diff) | |
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/shifter_operand.ll')
| -rw-r--r-- | test/CodeGen/ARM/shifter_operand.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/ARM/shifter_operand.ll b/test/CodeGen/ARM/shifter_operand.ll index 897fb1af01..01e3a922f6 100644 --- a/test/CodeGen/ARM/shifter_operand.ll +++ b/test/CodeGen/ARM/shifter_operand.ll @@ -36,8 +36,8 @@ entry: ; lsl #2 is free ; A9: test3: -; A9: ldr r1, [r1, r2, lsl #2] ; A9: ldr r0, [r0, r2, lsl #2] +; A9: ldr r1, [r1, r2, lsl #2] %tmp1 = shl i32 %offset, 2 %tmp2 = add i32 %base, %tmp1 %tmp3 = inttoptr i32 %tmp2 to i32* |