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authorJames Molloy <james.molloy@arm.com>2012-09-18 08:31:15 +0000
committerJames Molloy <james.molloy@arm.com>2012-09-18 08:31:15 +0000
commit97ecb83dffb5ff78ff84e9da21189268f52c63b2 (patch)
tree6a490c8d3123657b5d9e0b8a7d488a008f0d8af4 /test/CodeGen/ARM/domain-conv-vmovs.ll
parent3a3644436695d835bb4e1e2a0c7f3cc82a2807c2 (diff)
More domain conversion; convert VFP VMOVS to NEON instructions in more cases - when we may clobber the other S-lane by converting an S to a D instruction, make an effort to work out if the S lane is clobberable or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164114 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/domain-conv-vmovs.ll')
-rw-r--r--test/CodeGen/ARM/domain-conv-vmovs.ll20
1 files changed, 18 insertions, 2 deletions
diff --git a/test/CodeGen/ARM/domain-conv-vmovs.ll b/test/CodeGen/ARM/domain-conv-vmovs.ll
index e19185b0eb..18e169357b 100644
--- a/test/CodeGen/ARM/domain-conv-vmovs.ll
+++ b/test/CodeGen/ARM/domain-conv-vmovs.ll
@@ -79,6 +79,22 @@ define float @test_ineligible(float, float %in) {
; internal fault).
call void @bar()
; CHECL: bl bar
-; CHECK: vmov.f32 {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK: vext.32
+; CHECK: vext.32
ret float %val
-} \ No newline at end of file
+}
+
+define i32 @test_vmovs_no_sreg(i32 %in) {
+; CHECK: test_vmovs_no_sreg:
+
+ ; Check that the movement to and from GPRs takes place in the NEON domain.
+; CHECK: vmov.32 d
+ %x = bitcast i32 %in to float
+
+ %res = fadd float %x, %x
+
+; CHECK: vmov.32 r{{[0-9]+}}, d
+ %resi = bitcast float %res to i32
+
+ ret i32 %resi
+}