diff options
| author | Duraid Madina <duraid@octopus.com.au> | 2005-08-19 13:25:50 +0000 |
|---|---|---|
| committer | Duraid Madina <duraid@octopus.com.au> | 2005-08-19 13:25:50 +0000 |
| commit | a91103430bfc0d8439926e59cae2ac11e2254bff (patch) | |
| tree | 3a7aa99a8e5c7b0d1ad30f0927266f052381366c /lib | |
| parent | bfd4f55202743e0d7008840a28aff4179fa7993f (diff) | |
a bugfix (up top) and a quick repair job: disable generation of dep.z
(which died about a week ago) so we're back to load-(2^n-1)-then-AND
sequences. slow, but things should now be Almost Completely Working,
modulo those pesky alignment/ABI issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22904 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/IA64/IA64ISelPattern.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp index 35173f7a6c..a0a6f706e3 100644 --- a/lib/Target/IA64/IA64ISelPattern.cpp +++ b/lib/Target/IA64/IA64ISelPattern.cpp @@ -1220,7 +1220,7 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n"); case MVT::i16: depositPos=0; depositLen=16; break; case MVT::i32: depositPos=0; depositLen=32; break; } - BuildMI(BB, IA64::DEPZ, 1, Result).addReg(Tmp1) + BuildMI(BB, IA64::DEPZ, 3, Result).addReg(Tmp1) .addImm(depositPos).addImm(depositLen); return Result; } @@ -1439,7 +1439,7 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n"); case MVT::i32: case MVT::i64: { Tmp1 = SelectExpr(N.getOperand(0)); - switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) { +/* FIXME switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) { case 1: // ANDing a constant that is 2^n-1 for some n switch (Tmp3) { case 8: // if AND 0x00000000000000FF, be quaint and use zxt1 @@ -1457,7 +1457,7 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n"); break; } return Result; // early exit - } // fallthrough and emit a simple AND: + FIXME } */ // fallthrough and emit a simple AND: Tmp2 = SelectExpr(N.getOperand(1)); BuildMI(BB, IA64::AND, 2, Result).addReg(Tmp1).addReg(Tmp2); } |